sys/arch/i386/pci/pciide_gcsc_reg.h

34

#define GCSC_ATAC_GLD_MSR_CAP (GCSC_MSR_ATAC_BASE + 0)

sys/arch/i386/pci/pciide_gcsc_reg.h

35

#define GCSC_ATAC_GLD_MSR_CONFIG (GCSC_MSR_ATAC_BASE + 0x01)

sys/arch/i386/pci/pciide_gcsc_reg.h

36

#define GCSC_ATAC_GLD_MSR_SMI (GCSC_MSR_ATAC_BASE + 0x02)

sys/arch/i386/pci/pciide_gcsc_reg.h

37

#define GCSC_ATAC_GLD_MSR_ERROR (GCSC_MSR_ATAC_BASE + 0x03)

sys/arch/i386/pci/pciide_gcsc_reg.h

38

#define GCSC_ATAC_GLD_MSR_PM (GCSC_MSR_ATAC_BASE + 0x04)

sys/arch/i386/pci/pciide_gcsc_reg.h

39

#define GCSC_ATAC_GLD_MSR_DIAG (GCSC_MSR_ATAC_BASE + 0x05)

sys/arch/i386/pci/pciide_gcsc_reg.h

40

#define GCSC_ATAC_IO_BAR (GCSC_MSR_ATAC_BASE + 0x08)

sys/arch/i386/pci/pciide_gcsc_reg.h

41

#define GCSC_ATAC_RESET (GCSC_MSR_ATAC_BASE + 0x10)

sys/arch/i386/pci/pciide_gcsc_reg.h

42

#define GCSC_ATAC_CH0D0_PIO (GCSC_MSR_ATAC_BASE + 0x20)

sys/arch/i386/pci/pciide_gcsc_reg.h

43

#define GCSC_ATAC_CH0D0_DMA (GCSC_MSR_ATAC_BASE + 0x21)

sys/arch/i386/pci/pciide_gcsc_reg.h

44

#define GCSC_ATAC_CH0D1_PIO (GCSC_MSR_ATAC_BASE + 0x22)

sys/arch/i386/pci/pciide_gcsc_reg.h

45

#define GCSC_ATAC_CH0D1_DMA (GCSC_MSR_ATAC_BASE + 0x23)

sys/arch/i386/pci/pciide_gcsc_reg.h

46

#define GCSC_ATAC_PCI_ABRTERR (GCSC_MSR_ATAC_BASE + 0x24)