sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

730

int swizzle_mode = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

736

AMDGPU_TILING_GET(afb->tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

761

if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

764

int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

773

uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

859

AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

866

bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

891

AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

950

if (AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) == 1) /* LINEAR_ALIGNED */

sys/dev/pci/drm/amd/amdgpu/amdgpu_display.c

953

micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c

1148

AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

343

max_com = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

344

num_type = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

345

data_format = AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT);

sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c

347

AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_WRITE_COMPRESS_DISABLE);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1890

pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1980

if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1983

bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1984

bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1985

mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1986

tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1987

num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

2000

} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2007

if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2010

bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2011

bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2012

mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2013

tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2014

num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2022

} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

2026

pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1837

pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1919

if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1922

bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1923

bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1924

mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1925

tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1926

num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

1935

} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11678

linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11680

linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11682

linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11683

AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

11684

AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

184

if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

187

bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

188

bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

189

mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

190

tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

191

num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

204

} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

210

AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);