sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

538

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

550

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

563

tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

210

FMT_HIGHPASS_RANDOM_ENABLE, 0,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.c

275

FMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM,

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

107

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

178

OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

215

OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dce/dce_opp.h

251

type FMT_HIGHPASS_RANDOM_ENABLE; \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

132

FMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.c

70

FMT_HIGHPASS_RANDOM_ENABLE, 0,

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

112

type FMT_HIGHPASS_RANDOM_ENABLE; \

sys/dev/pci/drm/amd/display/dc/opp/dcn10/dcn10_opp.h

76

OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh), \

sys/dev/pci/drm/radeon/cik.c

8776

tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |

sys/dev/pci/drm/radeon/cik.c

8784

tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |

sys/dev/pci/drm/radeon/cik.c

8793

tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |

sys/dev/pci/drm/radeon/evergreen.c

1325

tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |

sys/dev/pci/drm/radeon/evergreen.c

1333

tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |