FIFO_ENABLE
outb(port + com_fifo, FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
outb(port + com_fifo, FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST |
sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8;
sc->sc_fifo = FIFO_ENABLE |
FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1);
com_write_reg(sc, com_fifo, FIFO_ENABLE);
FIFO_ENABLE | FIFO_ENABLE_64BYTE);
com_write_reg(sc, com_fifo, FIFO_ENABLE);
(FIFO_ENABLE | FIFO_TRIGGER_1) : 0;
fifo = FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST;
u_int8_t fifo = FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST;
u_int8_t fifo = FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST;
FIFO_ENABLE | FIFO_ENABLE_64BYTE |
FIFO_ENABLE |
FIFO_ENABLE, 1);
FIFO_ENABLE, 0);
SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, FIFO_ENABLE, mask_sh),\
type FIFO_ENABLE;\