Symbol: FD
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
68
FD(reg_name##__##field)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
44
FD(reg_name##__##field)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
43
FD(reg_name##__##field)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
40
FD(reg_name##__##field)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
56
FD(reg_name##__##field)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
65
FD(reg_name##__##field)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
57
FD(reg_name##__##field)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
56
FD(reg_name##__##field)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
265
FD(DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN), 1,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
266
FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN), gsl_params->gsl_master == tg->inst,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
267
FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY), HFLIP_READY_DELAY,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
270
FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY), HFLIP_CHECK_DELAY,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
272
FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE), 0,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
273
FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING), 1);
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
289
FD(DCP0_DCP_GSL_CONTROL__DCP_GSL0_EN), 0,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
290
FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN), 0,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
291
FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY), HFLIP_READY_DELAY,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
292
FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY), HFLIP_CHECK_DELAY,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
294
FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE), 0,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
295
FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING), 0);
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
331
FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT), trig_src_select,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
332
FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT), TRIGGER_POLARITY_SELECT_LOGIC_ZERO,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
333
FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL), rising_edge,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
334
FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL), falling_edge,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
336
FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT), 0,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
338
FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY), 0,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
340
FD(CRTC0_CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR), 1);
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
49
CRTC_REG_UPDATE_N(reg, 1, FD(reg##__##field), val)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
52
CRTC_REG_UPDATE_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
55
CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
561
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 1,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
562
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 1,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
563
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT), 0,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
564
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC), 0,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
565
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN), 0,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
566
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK), 0);
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
574
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 0,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
575
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 0,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
576
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT), 0,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
577
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC), 0,
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
578
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK), 0);
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
58
CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3, FD(reg##__##field4), val4)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
61
CRTC_REG_UPDATE_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3, FD(reg##__##field4), val4, FD(reg##__##field5), val5)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
64
CRTC_REG_SET_N(reg, 1, FD(reg##__##field), val)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
67
CRTC_REG_SET_N(reg, 2, FD(reg##__##field1), val1, FD(reg##__##field2), val2)
sys/dev/pci/drm/amd/display/dc/dce120/dce120_timing_generator.c
70
CRTC_REG_SET_N(reg, 3, FD(reg##__##field1), val1, FD(reg##__##field2), val2, FD(reg##__##field3), val3)
sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h
61
FD(reg_name##__##field)
sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h
47
#define FN(reg_name, field) FD(reg_name##__##field)