EVERGREEN_CRTC5_REGISTER_OFFSET
radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
EVERGREEN_CRTC5_REGISTER_OFFSET);
WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,
WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
EVERGREEN_CRTC5_REGISTER_OFFSET
EVERGREEN_VLINE_START_END + EVERGREEN_CRTC5_REGISTER_OFFSET
EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
EVERGREEN_CRTC5_REGISTER_OFFSET,
EVERGREEN_CRTC5_REGISTER_OFFSET);
EVERGREEN_CRTC5_REGISTER_OFFSET);
EVERGREEN_CRTC5_REGISTER_OFFSET