sys/dev/pci/drm/radeon/atombios_crtc.c

2246

radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;

sys/dev/pci/drm/radeon/cik.c

6888

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik.c

6901

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik.c

7240

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);

sys/dev/pci/drm/radeon/cik.c

7257

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/cik.c

7309

EVERGREEN_CRTC4_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/cik.c

7348

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/cik.c

7354

WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);

sys/dev/pci/drm/radeon/cik.c

7356

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);

sys/dev/pci/drm/radeon/evergreen.c

129

EVERGREEN_CRTC4_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/evergreen_cs.c

1034

EVERGREEN_VLINE_START_END + EVERGREEN_CRTC4_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/evergreen_cs.c

1042

EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/radeon_device.c

696

reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |

sys/dev/pci/drm/radeon/radeon_display.c

1509

EVERGREEN_CRTC4_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/radeon_display.c

1857

EVERGREEN_CRTC4_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/radeon_display.c

1859

EVERGREEN_CRTC4_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/si.c

146

EVERGREEN_CRTC4_REGISTER_OFFSET,