sys/dev/pci/drm/radeon/atombios_crtc.c

2243

radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;

sys/dev/pci/drm/radeon/cik.c

6885

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik.c

6898

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik.c

7237

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);

sys/dev/pci/drm/radeon/cik.c

7253

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/cik.c

7305

EVERGREEN_CRTC3_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/cik.c

7334

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/cik.c

7341

WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);

sys/dev/pci/drm/radeon/cik.c

7343

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);

sys/dev/pci/drm/radeon/evergreen.c

128

EVERGREEN_CRTC3_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/evergreen_cs.c

1033

EVERGREEN_VLINE_START_END + EVERGREEN_CRTC3_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/evergreen_cs.c

1041

EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/radeon_device.c

693

RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/radeon_display.c

1508

EVERGREEN_CRTC3_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/radeon_display.c

1850

EVERGREEN_CRTC3_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/radeon_display.c

1852

EVERGREEN_CRTC3_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/si.c

145

EVERGREEN_CRTC3_REGISTER_OFFSET,