sys/dev/pci/drm/radeon/atombios_crtc.c

2240

radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;

sys/dev/pci/drm/radeon/cik.c

6884

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik.c

6897

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik.c

7236

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);

sys/dev/pci/drm/radeon/cik.c

7251

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/cik.c

7303

EVERGREEN_CRTC2_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/cik.c

7331

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/cik.c

7337

WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);

sys/dev/pci/drm/radeon/cik.c

7339

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);

sys/dev/pci/drm/radeon/evergreen.c

127

EVERGREEN_CRTC2_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/evergreen_cs.c

1032

EVERGREEN_VLINE_START_END + EVERGREEN_CRTC2_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/evergreen_cs.c

1040

EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/radeon_device.c

692

reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |

sys/dev/pci/drm/radeon/radeon_display.c

1507

EVERGREEN_CRTC2_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/radeon_display.c

1843

EVERGREEN_CRTC2_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/radeon_display.c

1845

EVERGREEN_CRTC2_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/si.c

144

EVERGREEN_CRTC2_REGISTER_OFFSET,