sys/dev/pci/drm/radeon/atombios_crtc.c

2237

radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;

sys/dev/pci/drm/radeon/cik.c

6882

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik.c

6894

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik.c

7234

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);

sys/dev/pci/drm/radeon/cik.c

7247

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/cik.c

7300

EVERGREEN_CRTC1_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/cik.c

7318

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/cik.c

7325

WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);

sys/dev/pci/drm/radeon/cik.c

7327

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);

sys/dev/pci/drm/radeon/evergreen.c

126

EVERGREEN_CRTC1_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/evergreen_cs.c

1031

EVERGREEN_VLINE_START_END + EVERGREEN_CRTC1_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/evergreen_cs.c

1039

EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/radeon_device.c

690

RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/radeon_display.c

1506

EVERGREEN_CRTC1_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/radeon_display.c

1836

EVERGREEN_CRTC1_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/radeon_display.c

1838

EVERGREEN_CRTC1_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/si.c

143

EVERGREEN_CRTC1_REGISTER_OFFSET,