sys/dev/pci/drm/radeon/atombios_crtc.c

2234

radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;

sys/dev/pci/drm/radeon/cik.c

6881

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik.c

6893

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

sys/dev/pci/drm/radeon/cik.c

7233

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);

sys/dev/pci/drm/radeon/cik.c

7245

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/cik.c

7298

EVERGREEN_CRTC0_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/cik.c

7315

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/cik.c

7321

WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);

sys/dev/pci/drm/radeon/cik.c

7323

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);

sys/dev/pci/drm/radeon/evergreen.c

125

EVERGREEN_CRTC0_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/evergreen_cs.c

1030

EVERGREEN_VLINE_START_END + EVERGREEN_CRTC0_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/evergreen_cs.c

1038

EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/radeon_device.c

689

reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |

sys/dev/pci/drm/radeon/radeon_display.c

1505

EVERGREEN_CRTC0_REGISTER_OFFSET,

sys/dev/pci/drm/radeon/radeon_display.c

1829

EVERGREEN_CRTC0_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/radeon_display.c

1831

EVERGREEN_CRTC0_REGISTER_OFFSET);

sys/dev/pci/drm/radeon/si.c

142

EVERGREEN_CRTC0_REGISTER_OFFSET,