AMDGPU_MAX_MES_PIPES
for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++)
for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) {
for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) {
for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) {
struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES];
uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES];
uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES];
struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES];
uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES];
void *mqd_backup[AMDGPU_MAX_MES_PIPES];
struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES];
uint32_t sch_ctx_offs[AMDGPU_MAX_MES_PIPES];
uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES];
uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_PIPES];
uint32_t query_status_fence_offs[AMDGPU_MAX_MES_PIPES];
uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_PIPES];
uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_PIPES];
struct amdgpu_bo *resource_1[AMDGPU_MAX_MES_PIPES];
uint64_t resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES];
void *resource_1_addr[AMDGPU_MAX_MES_PIPES];
uint32_t fw_version[AMDGPU_MAX_MES_PIPES];
struct amdgpu_ring ring[AMDGPU_MAX_MES_PIPES];
spinlock_t ring_lock[AMDGPU_MAX_MES_PIPES];
const struct firmware *fw[AMDGPU_MAX_MES_PIPES];
struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES];
uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES];
uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES];
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
(AMDGPU_MAX_MES_PIPES * (AMDGPU_MES_LOG_BUFFER_SIZE + AMDGPU_MES_MSCRATCH_SIZE)) :
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {