EOWRITE4
EOWRITE4(&sc->sc, EHCI_USBMODE, usbmode);
EOWRITE4(&sc->sc, EHCI_USBCMD, val);
EOWRITE4(&sc->sc, EHCI_USBCMD, val);
EOWRITE4(&sc->sc, EHCI_USBMODE,
EOWRITE4(&sc->sc, EHCI_PORTSC(1),
EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
EOWRITE4(sc, EHCI_ASYNCLISTADDR,
EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR);
EOWRITE4(sc, EHCI_PORTSC(i),
EOWRITE4(sc, EHCI_USBCMD,
EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
EOWRITE4(sc, EHCI_USBMODE, usbmode);
EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) |
EOWRITE4(sc, port, v &~ EHCI_PS_PE);
EOWRITE4(sc, port, v &~ EHCI_PS_SUSP);
EOWRITE4(sc, port, v &~ EHCI_PS_PP);
EOWRITE4(sc, port, v &~ EHCI_PS_PIC);
EOWRITE4(sc, port, v | EHCI_PS_CSC);
EOWRITE4(sc, port, v | EHCI_PS_PEC);
EOWRITE4(sc, port, v | EHCI_PS_OCC);
EOWRITE4(sc, port, v | EHCI_PS_PE);
EOWRITE4(sc, port, v | EHCI_PS_SUSP);
EOWRITE4(sc, port, v | EHCI_PS_PR);
EOWRITE4(sc, port, v | EHCI_PS_PR);
EOWRITE4(sc, port, v & ~EHCI_PS_PR);
EOWRITE4(sc, port, v | EHCI_PS_PP);
EOWRITE4(sc, port, v | EHCI_PS_PIC);
EOWRITE4(sc, port, v | EHCI_PS_PO);
EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH);
EOWRITE4(sc, EHCI_USBCMD,
EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
EOWRITE4(sc, EHCI_PORTSC(i),
EOWRITE4(sc, EHCI_USBCMD, cmd);