ENVY_CCS_INT_MIDI0
reg &= ~ENVY_CCS_INT_MIDI0;
if (!(st & ENVY_MT_INTR_ALL) && !(mintr & ENVY_CCS_INT_MIDI0)) {
if (mintr & ENVY_CCS_INT_MIDI0) {
envy_ccs_write(sc, ENVY_CCS_INTSTAT, ENVY_CCS_INT_MIDI0);
reg &= ~ENVY_CCS_INT_MIDI0;
reg |= ENVY_CCS_INT_MIDI0;