EDCA_AC_VI
((tid == 4) || (tid == 5)) ? EDCA_AC_VI :
((tid == 4) || (tid == 5)) ? EDCA_AC_VI :
ic->ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 |
ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 |
ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 |
ic->ic_edca_ac[EDCA_AC_VI].ac_txoplimit);
case EDCA_AC_VI:
[EDCA_AC_VI] = { 4, 5, 2, 188 },
[EDCA_AC_VI] = { 3, 4, 2, 94 },
EDCA_AC_VI,
EDCA_AC_VI,
EDCA_AC_VI,
EDCA_AC_VI,
qid != usc->ep_data[EDCA_AC_VI] &&
AR_PIPE_TX_DATA, AR_PIPE_RX_DATA, &usc->ep_data[EDCA_AC_VI]);
ic->ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 |
ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 |
ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 |
ic->ic_edca_ac[EDCA_AC_VI].ac_txoplimit);
EXP2(edca[EDCA_AC_VI].ac_ecwmax) << 16 |
EXP2(edca[EDCA_AC_VI].ac_ecwmin));
AIFS(edca[EDCA_AC_VI].ac_aifsn) << 24 |
AIFS(edca[EDCA_AC_VI].ac_aifsn) >> 8);
edca[EDCA_AC_VI].ac_txoplimit);
ic->ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 |
ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 |
ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 |
ic->ic_edca_ac[EDCA_AC_VI].ac_txoplimit);
sc->ac2idx[EDCA_AC_VI] = (sc->ntx == 3) ? 1 : 0;
timeout_set(&ni->ni_addba_req_to[EDCA_AC_VI],
ieee80211_node_addba_request(ni, EDCA_AC_VI);
[EDCA_AC_VI] = { 4, 5, 2, 188 },
[EDCA_AC_VI] = { 3, 4, 2, 94 },
[EDCA_AC_VI] = { 3, 4, 2, 94 },
[EDCA_AC_VI] = { 3, 4, 2, 94 },
[EDCA_AC_VI] = { 3, 4, 2, 94 },
[EDCA_AC_VI] = { 3, 4, 2, 94 },
[EDCA_AC_VI] = { 4, 5, 1, 188 },
[EDCA_AC_VI] = { 3, 4, 1, 94 },
[EDCA_AC_VI] = { 3, 4, 1, 94 },
[EDCA_AC_VI] = { 3, 4, 1, 94 },
[EDCA_AC_VI] = { 3, 4, 1, 94 },
[EDCA_AC_VI] = { 3, 4, 1, 94 },
EDCA_AC_VI, /* CL */
EDCA_AC_VI, /* VI */
case EDCA_AC_VI:
ac = EDCA_AC_VI;
ac = EDCA_AC_VI;