EDCA_AC_BK
((tid == 1) || (tid == 2)) ? EDCA_AC_BK :
((tid == 1) || (tid == 2)) ? EDCA_AC_BK :
ic->ic_edca_ac[EDCA_AC_BK].ac_aifsn << 4 |
ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmin << 4 |
ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmax << 4 |
ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 |
[EDCA_AC_BK] = { 5, 10, 7, 0 },
[EDCA_AC_BK] = { 4, 10, 7, 0 },
EDCA_AC_BK,
EDCA_AC_BK,
EDCA_AC_BK,
EDCA_AC_BK,
qid != usc->ep_data[EDCA_AC_BK] &&
AR_PIPE_TX_DATA, AR_PIPE_RX_DATA, &usc->ep_data[EDCA_AC_BK]);
ic->ic_edca_ac[EDCA_AC_BK].ac_aifsn << 4 |
ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmin << 4 |
ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmax << 4 |
ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 |
EXP2(edca[EDCA_AC_BK].ac_ecwmax) << 16 |
EXP2(edca[EDCA_AC_BK].ac_ecwmin));
AIFS(edca[EDCA_AC_BK].ac_aifsn) << 12 |
edca[EDCA_AC_BK].ac_txoplimit << 16 |
ic->ic_edca_ac[EDCA_AC_BK].ac_aifsn << 4 |
ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmin << 4 |
ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmax << 4 |
ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 |
sc->ac2idx[EDCA_AC_BK] =
timeout_set(&ni->ni_addba_req_to[EDCA_AC_BK],
ieee80211_node_addba_request(ni, EDCA_AC_BK);
[EDCA_AC_BK] = { 5, 10, 7, 0 },
[EDCA_AC_BK] = { 4, 10, 7, 0 },
[EDCA_AC_BK] = { 4, 10, 7, 0 },
[EDCA_AC_BK] = { 4, 10, 7, 0 },
[EDCA_AC_BK] = { 4, 10, 7, 0 },
[EDCA_AC_BK] = { 4, 10, 7, 0 },
[EDCA_AC_BK] = { 5, 10, 7, 0 },
[EDCA_AC_BK] = { 4, 10, 7, 0 },
[EDCA_AC_BK] = { 4, 10, 7, 0 },
[EDCA_AC_BK] = { 4, 10, 7, 0 },
[EDCA_AC_BK] = { 4, 10, 7, 0 },
[EDCA_AC_BK] = { 4, 10, 7, 0 },
EDCA_AC_BK, /* BK */
EDCA_AC_BK, /* -- */
while (ac != EDCA_AC_BK && ic->ic_edca_ac[ac].ac_acm) {
case EDCA_AC_BK:
ac = EDCA_AC_BK;
ac = EDCA_AC_BK;