Symbol: DSC_SF
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
100
DSC_SF(DSCC0_DSCC_CONFIG0, ICH_RESET_AT_END_OF_LINE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
101
DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_PER_LINE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
102
DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
103
DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
104
DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
106
DSC_SF(DSCC0_DSCC_STATUS, DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
107
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
108
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
109
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
110
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
111
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
112
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
113
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
114
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
115
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
116
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
117
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
118
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
119
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
120
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
121
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
122
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
123
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
124
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
125
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
126
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
127
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
128
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
129
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
130
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
131
DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MINOR, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
132
DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MAJOR, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
133
DSC_SF(DSCC0_DSCC_PPS_CONFIG0, PPS_IDENTIFIER, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
134
DSC_SF(DSCC0_DSCC_PPS_CONFIG0, LINEBUF_DEPTH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
136
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BITS_PER_PIXEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
137
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, VBR_ENABLE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
138
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, SIMPLE_422, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
139
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CONVERT_RGB, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
140
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BLOCK_PRED_ENABLE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
141
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_422, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
142
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_420, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
143
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CHUNK_SIZE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
144
DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_WIDTH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
145
DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_HEIGHT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
146
DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_WIDTH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
147
DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_HEIGHT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
148
DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_XMIT_DELAY, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
149
DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_DEC_DELAY, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
150
DSC_SF(DSCC0_DSCC_PPS_CONFIG5, INITIAL_SCALE_VALUE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
151
DSC_SF(DSCC0_DSCC_PPS_CONFIG5, SCALE_INCREMENT_INTERVAL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
152
DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SCALE_DECREMENT_INTERVAL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
153
DSC_SF(DSCC0_DSCC_PPS_CONFIG6, FIRST_LINE_BPG_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
154
DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SECOND_LINE_BPG_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
155
DSC_SF(DSCC0_DSCC_PPS_CONFIG7, NFL_BPG_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
156
DSC_SF(DSCC0_DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
157
DSC_SF(DSCC0_DSCC_PPS_CONFIG8, NSL_BPG_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
158
DSC_SF(DSCC0_DSCC_PPS_CONFIG8, SECOND_LINE_OFFSET_ADJ, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
159
DSC_SF(DSCC0_DSCC_PPS_CONFIG9, INITIAL_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
160
DSC_SF(DSCC0_DSCC_PPS_CONFIG9, FINAL_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
161
DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MIN_QP, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
162
DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MAX_QP, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
163
DSC_SF(DSCC0_DSCC_PPS_CONFIG10, RC_MODEL_SIZE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
164
DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_EDGE_FACTOR, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
165
DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
166
DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
167
DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_LO, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
168
DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_HI, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
169
DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
170
DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
171
DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
172
DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
173
DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH4, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
174
DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH5, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
175
DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH6, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
176
DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH7, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
177
DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH8, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
178
DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH9, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
179
DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH10, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
180
DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH11, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
181
DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH12, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
182
DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH13, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
183
DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MIN_QP0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
184
DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MAX_QP0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
185
DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_BPG_OFFSET0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
186
DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
187
DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
188
DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
189
DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
190
DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
191
DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
192
DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
193
DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
194
DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
195
DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP4, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
196
DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP4, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
197
DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET4, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
198
DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP5, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
199
DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP5, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
200
DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET5, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
201
DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP6, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
202
DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP6, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
203
DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET6, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
204
DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP7, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
205
DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP7, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
206
DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET7, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
207
DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP8, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
208
DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP8, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
209
DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET8, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
210
DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP9, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
211
DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP9, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
212
DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET9, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
213
DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP10, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
214
DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP10, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
215
DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET10, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
216
DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP11, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
217
DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP11, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
218
DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET11, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
219
DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP12, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
220
DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP12, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
221
DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET12, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
222
DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP13, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
223
DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP13, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
224
DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET13, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
225
DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP14, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
226
DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP14, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
227
DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET14, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
228
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_DEFAULT_MEM_LOW_POWER_STATE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
229
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_FORCE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
230
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_DIS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
231
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_STATE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
232
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_FORCE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
233
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_DIS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
234
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_STATE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
235
DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC_R_Y_SQUARED_ERROR_LOWER, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
236
DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC_R_Y_SQUARED_ERROR_UPPER, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
237
DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC_G_CB_SQUARED_ERROR_LOWER, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
238
DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC_G_CB_SQUARED_ERROR_UPPER, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
239
DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC_B_CR_SQUARED_ERROR_LOWER, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
240
DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC_B_CR_SQUARED_ERROR_UPPER, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
241
DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_R_Y_MAX_ABS_ERROR, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
242
DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_G_CB_MAX_ABS_ERROR, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
243
DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR1, DSCC_B_CR_MAX_ABS_ERROR, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
244
DSC_SF(DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
245
DSC_SF(DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
246
DSC_SF(DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
247
DSC_SF(DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
248
DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
249
DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
250
DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
251
DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
252
DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS0_ROTATE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
253
DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS1_ROTATE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
254
DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS2_ROTATE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
255
DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS3_ROTATE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
256
DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
257
DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
258
DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
259
DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_PIXEL_FORMAT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
261
DSC_SF(DSCCIF0_DSCCIF_CONFIG0, DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
262
DSC_SF(DSCCIF0_DSCCIF_CONFIG1, PIC_WIDTH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
263
DSC_SF(DSCCIF0_DSCCIF_CONFIG1, PIC_HEIGHT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
264
DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
265
DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh)
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
95
DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_CLOCK_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
96
DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DISPCLK_R_GATE_DIS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
97
DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DSCCLK_R_GATE_DIS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
98
DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_DBG_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
99
DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_TEST_CLOCK_MUX_SEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.h
34
DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, mask_sh)
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
100
DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MAX_QP, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
101
DSC_SF(DSCC0_DSCC_PPS_CONFIG10, RC_MODEL_SIZE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
102
DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_EDGE_FACTOR, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
103
DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
104
DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
105
DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_LO, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
106
DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_HI, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
107
DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
108
DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
109
DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
110
DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
111
DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH4, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
112
DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH5, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
113
DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH6, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
114
DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH7, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
115
DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH8, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
116
DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH9, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
117
DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH10, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
118
DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH11, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
119
DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH12, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
120
DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH13, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
121
DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MIN_QP0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
122
DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MAX_QP0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
123
DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_BPG_OFFSET0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
124
DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
125
DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
126
DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
127
DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
128
DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
129
DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
130
DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
131
DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
132
DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
133
DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP4, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
134
DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP4, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
135
DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET4, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
136
DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP5, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
137
DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP5, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
138
DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET5, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
139
DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP6, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
140
DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP6, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
141
DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET6, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
142
DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP7, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
143
DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP7, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
144
DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET7, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
145
DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP8, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
146
DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP8, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
147
DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET8, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
148
DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP9, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
149
DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP9, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
150
DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET9, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
151
DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP10, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
152
DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP10, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
153
DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET10, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
154
DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP11, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
155
DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP11, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
156
DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET11, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
157
DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP12, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
158
DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP12, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
159
DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET12, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
160
DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP13, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
161
DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP13, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
162
DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET13, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
163
DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP14, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
164
DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP14, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
165
DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET14, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
166
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL0, DSCC_DEFAULT_MEM_LOW_POWER_STATE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
167
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL0, DSCC_MEM_PWR_FORCE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
168
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL0, DSCC_MEM_PWR_DIS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
169
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL0, DSCC_MEM_PWR_STATE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
17
DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_CLOCK_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
170
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL1, DSCC_DEFAULT_MEM_LOW_POWER_STATE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
171
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL1, DSCC_MEM_PWR_FORCE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
172
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL1, DSCC_MEM_PWR_DIS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
173
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL1, DSCC_MEM_PWR_STATE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
174
DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC_R_Y_SQUARED_ERROR_LOWER, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
175
DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC_R_Y_SQUARED_ERROR_UPPER, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
176
DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC_G_CB_SQUARED_ERROR_LOWER, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
177
DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC_G_CB_SQUARED_ERROR_UPPER, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
178
DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC_B_CR_SQUARED_ERROR_LOWER, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
179
DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC_B_CR_SQUARED_ERROR_UPPER, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
18
DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DISPCLK_R_GATE_DIS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
180
DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_R_Y_MAX_ABS_ERROR, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
181
DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_G_CB_MAX_ABS_ERROR, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
182
DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR1, DSCC_B_CR_MAX_ABS_ERROR, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
183
DSC_SF(DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0, DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
184
DSC_SF(DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1, DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
185
DSC_SF(DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2, DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
186
DSC_SF(DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3, DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
187
DSC_SF(DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0, DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
188
DSC_SF(DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1, DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
189
DSC_SF(DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2, DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
19
DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DSCCLK_R_GATE_DIS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
190
DSC_SF(DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3, DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
191
DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS0_ROTATE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
192
DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS1_ROTATE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
193
DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS2_ROTATE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
194
DSC_SF(DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE, DSCC_TEST_DEBUG_BUS3_ROTATE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
195
DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_PIXEL_FORMAT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
197
DSC_SF(DSCCIF0_DSCCIF_CONFIG0, DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
198
DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
199
DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
20
DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
200
DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, mask_sh)
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
21
DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_DBG_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
22
DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_TEST_CLOCK_MUX_SEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
23
DSC_SF(DSCC0_DSCC_CONFIG0, ICH_RESET_AT_END_OF_LINE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
24
DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_PER_LINE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
25
DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
26
DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
27
DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
29
DSC_SF(DSCC0_DSCC_STATUS, DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
30
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
31
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
32
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
33
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
34
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
35
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
36
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
37
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
38
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
39
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
40
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
41
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL0, DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
42
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
43
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
44
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
45
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
46
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
47
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
48
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
49
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
50
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
51
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
52
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
53
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
54
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
55
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
56
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
57
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
58
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
59
DSC_SF(DSCC0_DSCC_INTERRUPT_STATUS1, DSCC_END_OF_FRAME_NOT_REACHED_CLEAR, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
60
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
61
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
62
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
63
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
64
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
65
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
66
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
67
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
68
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL1, DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
69
DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MINOR, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
70
DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MAJOR, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
71
DSC_SF(DSCC0_DSCC_PPS_CONFIG0, PPS_IDENTIFIER, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
72
DSC_SF(DSCC0_DSCC_PPS_CONFIG0, LINEBUF_DEPTH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
74
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BITS_PER_PIXEL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
75
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, VBR_ENABLE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
76
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, SIMPLE_422, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
77
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CONVERT_RGB, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
78
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BLOCK_PRED_ENABLE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
79
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_422, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
80
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_420, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
81
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CHUNK_SIZE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
82
DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_WIDTH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
83
DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_HEIGHT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
84
DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_WIDTH, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
85
DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_HEIGHT, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
86
DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_XMIT_DELAY, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
87
DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_DEC_DELAY, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
88
DSC_SF(DSCC0_DSCC_PPS_CONFIG5, INITIAL_SCALE_VALUE, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
89
DSC_SF(DSCC0_DSCC_PPS_CONFIG5, SCALE_INCREMENT_INTERVAL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
90
DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SCALE_DECREMENT_INTERVAL, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
91
DSC_SF(DSCC0_DSCC_PPS_CONFIG6, FIRST_LINE_BPG_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
92
DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SECOND_LINE_BPG_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
93
DSC_SF(DSCC0_DSCC_PPS_CONFIG7, NFL_BPG_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
94
DSC_SF(DSCC0_DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
95
DSC_SF(DSCC0_DSCC_PPS_CONFIG8, NSL_BPG_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
96
DSC_SF(DSCC0_DSCC_PPS_CONFIG8, SECOND_LINE_OFFSET_ADJ, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
97
DSC_SF(DSCC0_DSCC_PPS_CONFIG9, INITIAL_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
98
DSC_SF(DSCC0_DSCC_PPS_CONFIG9, FINAL_OFFSET, mask_sh), \
sys/dev/pci/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h
99
DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MIN_QP, mask_sh), \