sys/dev/pci/drm/i915/display/i9xx_plane.c

1191

val = intel_de_read(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

516

intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);

sys/dev/pci/drm/i915/display/i9xx_plane.c

559

intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);

sys/dev/pci/drm/i915/display/i9xx_plane.c

574

error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

586

error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

597

error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

615

intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);

sys/dev/pci/drm/i915/display/i9xx_plane.c

741

val = intel_de_read(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

914

dspcntr = intel_de_read_fw(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/i9xx_plane.c

916

intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);

sys/dev/pci/drm/i915/display/intel_color.c

1070

tmp = intel_de_read(display, DSPCNTR(display, i9xx_plane));

sys/dev/pci/drm/i915/display/intel_display.c

8321

intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE);

sys/dev/pci/drm/i915/display/intel_display.c

8323

intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE);

sys/dev/pci/drm/i915/display/intel_display.c

8325

intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1320

info->ctrl_reg = DSPCNTR(display, info->pipe);

sys/dev/pci/drm/i915/gvt/cmd_parser.c

1387

info->ctrl_reg = DSPCNTR(display, info->pipe);

sys/dev/pci/drm/i915/gvt/display.c

204

vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;

sys/dev/pci/drm/i915/gvt/display.c

518

vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) &= ~DISP_ENABLE;

sys/dev/pci/drm/i915/gvt/fb_decoder.c

224

val = vgpu_vreg_t(vgpu, DSPCNTR(display, pipe));

sys/dev/pci/drm/i915/gvt/handlers.c

1037

if (vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) & PLANE_CTL_ASYNC_FLIP)

sys/dev/pci/drm/i915/intel_clock_gating.c

139

intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe),

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

176

MMIO_D(DSPCNTR(display, PIPE_A));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

185

MMIO_D(DSPCNTR(display, PIPE_B));

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

194

MMIO_D(DSPCNTR(display, PIPE_C));