sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

323

if (enc110->se_mask->DP_VID_N_MUL)

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

324

REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

365

SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh)

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

494

uint8_t DP_VID_N_MUL;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

626

uint32_t DP_VID_N_MUL;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1001

DP_VID_N_MUL, n_multiply);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

341

SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

511

type DP_VID_N_MUL;\

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

511

DP_VID_N_MUL, n_multiply);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

211

SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

342

DP_VID_N_MUL, n_multiply);

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

196

SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

290

DP_VID_N_MUL, n_multiply);

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.h

117

SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

322

DP_VID_N_MUL, n_multiply);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

197

SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\