sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

975

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c

985

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

166

SE_SF(DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

246

SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

440

uint8_t DP_VID_M_N_GEN_EN;

sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h

572

uint32_t DP_VID_M_N_GEN_EN;

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

1000

DP_VID_M_N_GEN_EN, 1,

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c

989

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

238

SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

454

type DP_VID_M_N_GEN_EN;\

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

499

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

510

DP_VID_M_N_GEN_EN, 1,

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

148

SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

330

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

341

DP_VID_M_N_GEN_EN, 1,

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

149

SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

278

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

289

DP_VID_M_N_GEN_EN, 1,

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.h

70

SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

310

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.c

321

DP_VID_M_N_GEN_EN, 1,

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

150

SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

293

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c

319

REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);

sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h

72

SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\