sys/dev/pci/drm/i915/display/intel_ddi.c

3823

temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;

sys/dev/pci/drm/i915/display/intel_ddi.c

3853

DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE);

sys/dev/pci/drm/i915/display/intel_display_regs.h

2304

#define DP_TP_CTL_LINK_TRAIN_PAT1 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 0)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2305

#define DP_TP_CTL_LINK_TRAIN_PAT2 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 1)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2306

#define DP_TP_CTL_LINK_TRAIN_PAT3 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 4)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2307

#define DP_TP_CTL_LINK_TRAIN_PAT4 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 5)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2308

#define DP_TP_CTL_LINK_TRAIN_IDLE REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 2)

sys/dev/pci/drm/i915/display/intel_display_regs.h

2309

#define DP_TP_CTL_LINK_TRAIN_NORMAL REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 3)

sys/dev/pci/drm/i915/display/intel_dp_test.c

237

DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK,

sys/dev/pci/drm/i915/display/intel_dp_test.c

298

DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK,