Symbol: DP_SEC_TIMESTAMP_MODE
sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c
1700
tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1);
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1353
REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
198
SE_SF(DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
276
SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
470
uint8_t DP_SEC_TIMESTAMP_MODE;
sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.h
602
uint32_t DP_SEC_TIMESTAMP_MODE;
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
1342
REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
270
SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
486
type DP_SEC_TIMESTAMP_MODE;\
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c
742
REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h
165
SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h
163
SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.h
84
SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h
164
SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
sys/dev/pci/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.h
86
SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\