sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

80

{ 0, DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR1) - 1},

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

81

{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR1), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR2) - 1 },

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

88

{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR8), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1) - 1 },

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dpcd.c

92

{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1) - 1 },

sys/dev/pci/drm/display/drm_dp_helper.c

2660

if (drm_WARN_ON(aux->drm_dev, dp_phy < DP_PHY_LTTPR1 || dp_phy > DP_MAX_LTTPR_COUNT))

sys/dev/pci/drm/display/drm_dp_helper.c

423

[DP_PHY_LTTPR1] = "LTTPR 1",

sys/dev/pci/drm/i915/display/intel_dp_link_training.c

76

return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1];

sys/dev/pci/drm/include/drm/display/drm_dp.h

1526

#define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i))

sys/dev/pci/drm/include/drm/display/drm_dp.h

1532

((dp_phy) - DP_PHY_LTTPR1))

sys/dev/pci/drm/include/drm/display/drm_dp.h

1535

(DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))

sys/dev/pci/drm/include/drm/display/drm_dp.h

1583

((dp_phy) - DP_PHY_LTTPR1)))

sys/dev/pci/drm/include/drm/display/drm_dp.h

1586

(DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg)