DP_PHY_DPRX
if (dp_phy == DP_PHY_DPRX) {
[DP_PHY_DPRX] = "DPRX",
if (dp_phy == DP_PHY_DPRX)
DP_PHY_DPRX, DP_TRAINING_PATTERN_1);
intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
lt_dbg(intel_dp, DP_PHY_DPRX, "LTTPR common capabilities: %*ph\n",
lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to read sink status\n");
intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,
lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n");
lt_dbg(intel_dp, DP_PHY_DPRX,
lt_dbg(intel_dp, DP_PHY_DPRX,
lt_dbg(intel_dp, DP_PHY_DPRX,
lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n");
lt_dbg(intel_dp, DP_PHY_DPRX,
ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX,
lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS1\n");
lt_err(intel_dp, DP_PHY_DPRX, "Failed to read TX FFE presets\n");
intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);
if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
lt_err(intel_dp, DP_PHY_DPRX, "Failed to set initial TX FFE settings\n");
if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX,
lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2\n");
lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
lt_err(intel_dp, DP_PHY_DPRX,
lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n");
intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
lt_err(intel_dp, DP_PHY_DPRX, "Lane channel eq timeout\n");
intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);
if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n");
intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
lt_err(intel_dp, DP_PHY_DPRX, "Max loop count reached\n");
lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n");
lt_dbg(intel_dp, DP_PHY_DPRX, "Interlane align done\n");
intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
lt_err(intel_dp, DP_PHY_DPRX, "Interlane align timeout\n");
lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2 CDS\n");
lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n");
intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n");
intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
lt_err(intel_dp, DP_PHY_DPRX, "CDS timeout\n");
lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n");
lt_dbg(intel_dp, DP_PHY_DPRX,
DP_PHY_DPRX, DP_TRAINING_PATTERN_2);
intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n");
lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n");
lt_err(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after failure\n");
lt_dbg(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after forced failure\n");
lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n");
lt_dbg(intel_dp, DP_PHY_DPRX,
lttpr_count <= 0 && dp_phy != DP_PHY_DPRX);
return dp_phy == DP_PHY_DPRX ?
int reg = dp_phy == DP_PHY_DPRX ?
sink_tps4 = dp_phy != DP_PHY_DPRX ||
sink_tps3 = dp_phy != DP_PHY_DPRX ||
lt_dbg(intel_dp, DP_PHY_DPRX, "Reloading eDP link rates\n");
lt_dbg(intel_dp, DP_PHY_DPRX, "Using LINK_BW_SET value %02x\n",
lt_dbg(intel_dp, DP_PHY_DPRX,
if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);