sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h

528

type DP_DSC_MODE;\

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

288

DP_DSC_MODE, dsc_mode,

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c

356

REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);

sys/dev/pci/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.h

70

SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

311

DP_DSC_MODE, dsc_mode,

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c

392

REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);

sys/dev/pci/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.h

258

SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

399

REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c

410

REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);

sys/dev/pci/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.h

243

SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

361

REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1);

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c

372

REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);

sys/dev/pci/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.h

164

SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dio/dcn35/dcn35_dio_stream_encoder.h

244

SE_SF(DP0_DP_DSC_CNTL, DP_DSC_MODE, mask_sh),\