sys/dev/pci/drm/i915/display/intel_display_power_well.c

536

intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch),

sys/dev/pci/drm/i915/display/intel_dp_aux.c

596

return DP_AUX_CH_CTL(aux_ch);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

599

return DP_AUX_CH_CTL(AUX_CH_B);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

626

return DP_AUX_CH_CTL(aux_ch);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

633

return DP_AUX_CH_CTL(AUX_CH_A);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

667

return DP_AUX_CH_CTL(aux_ch);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

670

return DP_AUX_CH_CTL(AUX_CH_A);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

708

return DP_AUX_CH_CTL(aux_ch);

sys/dev/pci/drm/i915/display/intel_dp_aux.c

711

return DP_AUX_CH_CTL(AUX_CH_A);

sys/dev/pci/drm/i915/gvt/handlers.c

1097

if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A)))

sys/dev/pci/drm/i915/gvt/handlers.c

1100

reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B)))

sys/dev/pci/drm/i915/gvt/handlers.c

1103

reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C)))

sys/dev/pci/drm/i915/gvt/handlers.c

1106

reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D)))

sys/dev/pci/drm/i915/gvt/handlers.c

1200

offset != i915_mmio_reg_offset(DP_AUX_CH_CTL(port_index))) {

sys/dev/pci/drm/i915/gvt/handlers.c

1206

DP_AUX_CH_CTL(port_index))) {

sys/dev/pci/drm/i915/gvt/handlers.c

2367

MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4, 0, 0, 0, D_ALL, NULL,

sys/dev/pci/drm/i915/gvt/handlers.c

2616

MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,

sys/dev/pci/drm/i915/gvt/handlers.c

2618

MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,

sys/dev/pci/drm/i915/gvt/handlers.c

2620

MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

528

MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

923

MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

924

MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4);

sys/dev/pci/drm/i915/intel_gvt_mmio_table.c

925

MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4);