sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

401

.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \

sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

418

.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

463

.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \

sys/dev/pci/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

448

.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \

sys/dev/pci/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

768

.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \

sys/dev/pci/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

729

.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \

sys/dev/pci/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

521

.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \

sys/dev/pci/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

527

.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \

sys/dev/pci/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

524

.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \

sys/dev/pci/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

515

.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

398

SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \

sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

399

SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

396

SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \

sys/dev/pci/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

397

SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\

sys/dev/pci/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

416

SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \

sys/dev/pci/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

396

SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \

sys/dev/pci/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

397

SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

375

SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \

sys/dev/pci/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

376

SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)