sys/dev/pci/drm/i915/display/g4x_dp.c

186

bool cur_state = intel_de_read(display, DP_A) & EDP_PLL_ENABLE;

sys/dev/pci/drm/i915/display/g4x_dp.c

215

intel_de_write(display, DP_A, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

216

intel_de_posting_read(display, DP_A);

sys/dev/pci/drm/i915/display/g4x_dp.c

230

intel_de_write(display, DP_A, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

231

intel_de_posting_read(display, DP_A);

sys/dev/pci/drm/i915/display/g4x_dp.c

248

intel_de_write(display, DP_A, intel_dp->DP);

sys/dev/pci/drm/i915/display/g4x_dp.c

249

intel_de_posting_read(display, DP_A);

sys/dev/pci/drm/i915/display/g4x_dp.c

395

if ((intel_de_read(display, DP_A) & EDP_PLL_FREQ_MASK) == EDP_PLL_FREQ_162MHZ)

sys/dev/pci/drm/i915/display/intel_display.c

7721

if ((intel_de_read(display, DP_A) & DP_DETECTED) == 0)

sys/dev/pci/drm/i915/display/intel_display.c

7790

g4x_dp_init(display, DP_A, PORT_A);

sys/dev/pci/drm/i915/display/intel_pps.c

1862

g4x_dp_port_enabled(display, DP_A, PORT_A, &panel_pipe);