sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

717

dp_set_hw_lane_settings(link, &pipe_ctx->link_res, p_link_settings, DPRX);

sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c

719

dpcd_set_lane_settings(link, p_link_settings, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

128

dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_phy.c

135

dpcd_set_lane_settings(link, lt_settings, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c

1452

DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

105

lt_settings->pattern_for_eq, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

112

&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

127

dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

149

&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

178

&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

86

dp_set_hw_training_pattern(link, link_res, lt_settings->pattern_for_cr, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

94

&dpcd_lane_status_updated, dpcd_lane_adjust, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

97

dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c

98

dp_set_hw_training_pattern(link, link_res, lt_settings->pattern_for_eq, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

207

dp_set_hw_training_pattern(link, link_res, DP_TRAINING_PATTERN_SEQUENCE_2, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

209

dp_set_hw_lane_settings(link, link_res, lt_settings, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

435

start_clock_recovery_pattern_early(link, link_res, lt_settings, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

479

status = perform_8b_10b_clock_recovery_sequence(link, link_res, lt_settings, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

484

DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_auxless.c

53

dp_set_hw_training_pattern(link, link_res, lt_settings.pattern_for_cr, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_auxless.c

56

dp_set_hw_lane_settings(link, link_res, &lt_settings, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_auxless.c

64

dp_set_hw_training_pattern(link, link_res, lt_settings.pattern_for_eq, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_auxless.c

67

dp_set_hw_lane_settings(link, link_res, &lt_settings, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

243

if (hop != DPRX)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

254

if (hop != DPRX) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

485

status = dpcd_set_lt_pattern(link, lt_settings->pattern_for_cr, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

501

DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

540

DPRX,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

604

if (hop == DPRX)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

667

if (hop == DPRX && retries_eq == 1)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

743

wait_time_microsec = dpia_get_eq_aux_rd_interval(link, lt_settings, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

748

status = dpcd_set_lt_pattern(link, tr_pattern, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

764

DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

795

DPRX,

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

834

if (hop != DPRX)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

890

if (hop == DPRX && result != LINK_TRAINING_ABORT) {

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

927

else if (hop == DPRX)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c

959

if (hop != DPRX)

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

126

start_clock_recovery_pattern_early(link, link_res, lt_settings, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

177

status = perform_8b_10b_clock_recovery_sequence(link, link_res, lt_settings, DPRX);

sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c

182

DPRX);