sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1126

tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

1133

tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

169

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

199

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

237

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

250

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

283

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.c

301

REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

135

uint32_t DPG_WATERMARK_MASK_CONTROL;

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

269

SFB(blk, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

270

SFB(blk, DPG_WATERMARK_MASK_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

280

SFB(blk, DPG_WATERMARK_MASK_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

315

SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\

sys/dev/pci/drm/amd/display/dc/dce/dce_mem_input.h

52

SRI(DPG_WATERMARK_MASK_CONTROL, DMIF_PG, id),\

sys/dev/pci/drm/radeon/cik.c

9352

wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/cik.c

9356

WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/cik.c

9361

tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);

sys/dev/pci/drm/radeon/cik.c

9364

WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/pci/drm/radeon/cik.c

9369

WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask);