Symbol: DMUB_SR
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
100
DMUB_SR(DMCUB_SCRATCH8) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
101
DMUB_SR(DMCUB_SCRATCH9) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
102
DMUB_SR(DMCUB_SCRATCH10) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
103
DMUB_SR(DMCUB_SCRATCH11) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
104
DMUB_SR(DMCUB_SCRATCH12) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
105
DMUB_SR(DMCUB_SCRATCH13) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
106
DMUB_SR(DMCUB_SCRATCH14) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
107
DMUB_SR(DMCUB_SCRATCH15) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
108
DMUB_SR(DMCUB_GPINT_DATAIN1) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
109
DMUB_SR(CC_DC_PIPE_DIS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
110
DMUB_SR(MMHUBBUB_SOFT_RESET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
111
DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
112
DMUB_SR(DCN_VM_FB_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
113
DMUB_SR(DMCUB_INTERRUPT_ACK) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
114
DMUB_SR(DMCUB_TIMER_CURRENT) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
115
DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
116
DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
117
DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
36
DMUB_SR(DMCUB_CNTL) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
37
DMUB_SR(DMCUB_MEM_CNTL) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
38
DMUB_SR(DMCUB_SEC_CNTL) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
39
DMUB_SR(DMCUB_INBOX0_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
40
DMUB_SR(DMCUB_INBOX0_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
41
DMUB_SR(DMCUB_INBOX0_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
42
DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
43
DMUB_SR(DMCUB_INBOX1_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
44
DMUB_SR(DMCUB_INBOX1_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
45
DMUB_SR(DMCUB_INBOX1_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
46
DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
47
DMUB_SR(DMCUB_OUTBOX0_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
48
DMUB_SR(DMCUB_OUTBOX0_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
49
DMUB_SR(DMCUB_OUTBOX0_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
50
DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
51
DMUB_SR(DMCUB_OUTBOX1_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
52
DMUB_SR(DMCUB_OUTBOX1_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
53
DMUB_SR(DMCUB_OUTBOX1_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
54
DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
55
DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
56
DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
57
DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
58
DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
59
DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
60
DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
61
DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
62
DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
63
DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
64
DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
65
DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
66
DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
67
DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
68
DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
69
DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
70
DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
71
DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
72
DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
73
DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
74
DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
75
DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
76
DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
77
DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
78
DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
79
DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
80
DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
81
DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
82
DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
83
DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
84
DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
85
DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
86
DMUB_SR(DMCUB_REGION4_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
87
DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
88
DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
89
DMUB_SR(DMCUB_REGION5_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
90
DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
91
DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
92
DMUB_SR(DMCUB_SCRATCH0) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
93
DMUB_SR(DMCUB_SCRATCH1) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
94
DMUB_SR(DMCUB_SCRATCH2) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
95
DMUB_SR(DMCUB_SCRATCH3) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
96
DMUB_SR(DMCUB_SCRATCH4) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
97
DMUB_SR(DMCUB_SCRATCH5) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
98
DMUB_SR(DMCUB_SCRATCH6) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn20.h
99
DMUB_SR(DMCUB_SCRATCH7) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
100
DMUB_SR(DMCUB_SCRATCH8) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
101
DMUB_SR(DMCUB_SCRATCH9) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
102
DMUB_SR(DMCUB_SCRATCH10) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
103
DMUB_SR(DMCUB_SCRATCH11) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
104
DMUB_SR(DMCUB_SCRATCH12) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
105
DMUB_SR(DMCUB_SCRATCH13) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
106
DMUB_SR(DMCUB_SCRATCH14) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
107
DMUB_SR(DMCUB_SCRATCH15) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
108
DMUB_SR(DMCUB_GPINT_DATAIN1) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
109
DMUB_SR(DMCUB_GPINT_DATAOUT) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
110
DMUB_SR(CC_DC_PIPE_DIS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
111
DMUB_SR(MMHUBBUB_SOFT_RESET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
112
DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
113
DMUB_SR(DCN_VM_FB_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
114
DMUB_SR(DMCUB_TIMER_CURRENT) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
115
DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
116
DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
117
DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
118
DMUB_SR(DMCUB_INTERRUPT_ENABLE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
119
DMUB_SR(DMCUB_INTERRUPT_ACK)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
36
DMUB_SR(DMCUB_CNTL) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
37
DMUB_SR(DMCUB_CNTL2) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
38
DMUB_SR(DMCUB_SEC_CNTL) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
39
DMUB_SR(DMCUB_INBOX0_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
40
DMUB_SR(DMCUB_INBOX0_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
41
DMUB_SR(DMCUB_INBOX0_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
42
DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
43
DMUB_SR(DMCUB_INBOX1_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
44
DMUB_SR(DMCUB_INBOX1_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
45
DMUB_SR(DMCUB_INBOX1_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
46
DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
47
DMUB_SR(DMCUB_OUTBOX0_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
48
DMUB_SR(DMCUB_OUTBOX0_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
49
DMUB_SR(DMCUB_OUTBOX0_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
50
DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
51
DMUB_SR(DMCUB_OUTBOX1_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
52
DMUB_SR(DMCUB_OUTBOX1_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
53
DMUB_SR(DMCUB_OUTBOX1_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
54
DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
55
DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
56
DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
57
DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
58
DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
59
DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
60
DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
61
DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
62
DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
63
DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
64
DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
65
DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
66
DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
67
DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
68
DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
69
DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
70
DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
71
DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
72
DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
73
DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
74
DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
75
DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
76
DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
77
DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
78
DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
79
DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
80
DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
81
DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
82
DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
83
DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
84
DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
85
DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
86
DMUB_SR(DMCUB_REGION4_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
87
DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
88
DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
89
DMUB_SR(DMCUB_REGION5_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
90
DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
91
DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
92
DMUB_SR(DMCUB_SCRATCH0) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
93
DMUB_SR(DMCUB_SCRATCH1) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
94
DMUB_SR(DMCUB_SCRATCH2) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
95
DMUB_SR(DMCUB_SCRATCH3) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
96
DMUB_SR(DMCUB_SCRATCH4) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
97
DMUB_SR(DMCUB_SCRATCH5) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
98
DMUB_SR(DMCUB_SCRATCH6) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn31.h
99
DMUB_SR(DMCUB_SCRATCH7) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
100
DMUB_SR(DMCUB_SCRATCH5) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
101
DMUB_SR(DMCUB_SCRATCH6) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
102
DMUB_SR(DMCUB_SCRATCH7) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
103
DMUB_SR(DMCUB_SCRATCH8) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
104
DMUB_SR(DMCUB_SCRATCH9) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
105
DMUB_SR(DMCUB_SCRATCH10) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
106
DMUB_SR(DMCUB_SCRATCH11) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
107
DMUB_SR(DMCUB_SCRATCH12) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
108
DMUB_SR(DMCUB_SCRATCH13) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
109
DMUB_SR(DMCUB_SCRATCH14) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
110
DMUB_SR(DMCUB_SCRATCH15) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
111
DMUB_SR(DMCUB_SCRATCH16) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
112
DMUB_SR(DMCUB_SCRATCH17) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
113
DMUB_SR(DMCUB_SCRATCH18) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
114
DMUB_SR(DMCUB_SCRATCH19) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
115
DMUB_SR(DMCUB_SCRATCH20) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
116
DMUB_SR(DMCUB_SCRATCH21) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
117
DMUB_SR(DMCUB_SCRATCH22) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
118
DMUB_SR(DMCUB_SCRATCH23) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
119
DMUB_SR(DMCUB_GPINT_DATAIN0) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
120
DMUB_SR(DMCUB_GPINT_DATAIN1) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
121
DMUB_SR(DMCUB_GPINT_DATAOUT) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
122
DMUB_SR(CC_DC_PIPE_DIS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
123
DMUB_SR(MMHUBBUB_SOFT_RESET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
124
DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
125
DMUB_SR(DCN_VM_FB_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
126
DMUB_SR(DMCUB_TIMER_CURRENT) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
127
DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
128
DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
129
DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
130
DMUB_SR(DMCUB_REGION3_TMR_AXI_SPACE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
131
DMUB_SR(DMCUB_INTERRUPT_ENABLE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
132
DMUB_SR(DMCUB_INTERRUPT_ACK)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
36
DMUB_SR(DMCUB_CNTL) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
37
DMUB_SR(DMCUB_CNTL2) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
38
DMUB_SR(DMCUB_SEC_CNTL) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
39
DMUB_SR(DMCUB_INBOX0_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
40
DMUB_SR(DMCUB_INBOX0_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
41
DMUB_SR(DMCUB_INBOX0_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
42
DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
43
DMUB_SR(DMCUB_INBOX1_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
44
DMUB_SR(DMCUB_INBOX1_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
45
DMUB_SR(DMCUB_INBOX1_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
46
DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
47
DMUB_SR(DMCUB_OUTBOX0_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
48
DMUB_SR(DMCUB_OUTBOX0_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
49
DMUB_SR(DMCUB_OUTBOX0_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
50
DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
51
DMUB_SR(DMCUB_OUTBOX1_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
52
DMUB_SR(DMCUB_OUTBOX1_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
53
DMUB_SR(DMCUB_OUTBOX1_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
54
DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
55
DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
56
DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
57
DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
58
DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
59
DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
60
DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
61
DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
62
DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
63
DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
64
DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
65
DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
66
DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
67
DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
68
DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
69
DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
70
DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
71
DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
72
DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
73
DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
74
DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
75
DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
76
DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
77
DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
78
DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
79
DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
80
DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
81
DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
82
DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
83
DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
84
DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
85
DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
86
DMUB_SR(DMCUB_REGION4_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
87
DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
88
DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
89
DMUB_SR(DMCUB_REGION5_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
90
DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
91
DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
92
DMUB_SR(DMCUB_REGION6_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
93
DMUB_SR(DMCUB_REGION6_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
94
DMUB_SR(DMCUB_REGION6_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
95
DMUB_SR(DMCUB_SCRATCH0) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
96
DMUB_SR(DMCUB_SCRATCH1) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
97
DMUB_SR(DMCUB_SCRATCH2) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
98
DMUB_SR(DMCUB_SCRATCH3) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn32.h
99
DMUB_SR(DMCUB_SCRATCH4) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
100
DMUB_SR(DMCUB_SCRATCH5) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
101
DMUB_SR(DMCUB_SCRATCH6) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
102
DMUB_SR(DMCUB_SCRATCH7) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
103
DMUB_SR(DMCUB_SCRATCH8) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
104
DMUB_SR(DMCUB_SCRATCH9) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
105
DMUB_SR(DMCUB_SCRATCH10) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
106
DMUB_SR(DMCUB_SCRATCH11) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
107
DMUB_SR(DMCUB_SCRATCH12) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
108
DMUB_SR(DMCUB_SCRATCH13) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
109
DMUB_SR(DMCUB_SCRATCH14) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
110
DMUB_SR(DMCUB_SCRATCH15) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
111
DMUB_SR(DMCUB_SCRATCH16) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
112
DMUB_SR(DMCUB_SCRATCH17) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
113
DMUB_SR(DMCUB_SCRATCH18) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
114
DMUB_SR(DMCUB_SCRATCH19) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
115
DMUB_SR(DMCUB_SCRATCH20) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
116
DMUB_SR(DMCUB_SCRATCH21) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
117
DMUB_SR(DMCUB_GPINT_DATAIN0) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
118
DMUB_SR(DMCUB_GPINT_DATAIN1) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
119
DMUB_SR(DMCUB_GPINT_DATAOUT) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
120
DMUB_SR(CC_DC_PIPE_DIS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
121
DMUB_SR(MMHUBBUB_SOFT_RESET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
122
DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
123
DMUB_SR(DCN_VM_FB_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
124
DMUB_SR(DMCUB_TIMER_CURRENT) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
125
DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
126
DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
127
DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
128
DMUB_SR(DMCUB_REGION3_TMR_AXI_SPACE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
129
DMUB_SR(DMCUB_INTERRUPT_ENABLE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
130
DMUB_SR(DMCUB_INTERRUPT_ACK) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
131
DMUB_SR(DMU_CLK_CNTL)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
36
DMUB_SR(DMCUB_CNTL) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
37
DMUB_SR(DMCUB_CNTL2) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
38
DMUB_SR(DMCUB_SEC_CNTL) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
39
DMUB_SR(DMCUB_INBOX0_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
40
DMUB_SR(DMCUB_INBOX0_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
41
DMUB_SR(DMCUB_INBOX0_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
42
DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
43
DMUB_SR(DMCUB_INBOX1_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
44
DMUB_SR(DMCUB_INBOX1_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
45
DMUB_SR(DMCUB_INBOX1_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
46
DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
47
DMUB_SR(DMCUB_OUTBOX0_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
48
DMUB_SR(DMCUB_OUTBOX0_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
49
DMUB_SR(DMCUB_OUTBOX0_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
50
DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
51
DMUB_SR(DMCUB_OUTBOX1_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
52
DMUB_SR(DMCUB_OUTBOX1_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
53
DMUB_SR(DMCUB_OUTBOX1_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
54
DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
55
DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
56
DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
57
DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
58
DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
59
DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
60
DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
61
DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
62
DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
63
DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
64
DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
65
DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
66
DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
67
DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
68
DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
69
DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
70
DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
71
DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
72
DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
73
DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
74
DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
75
DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
76
DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
77
DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
78
DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
79
DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
80
DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
81
DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
82
DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
83
DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
84
DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
85
DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
86
DMUB_SR(DMCUB_REGION4_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
87
DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
88
DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
89
DMUB_SR(DMCUB_REGION5_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
90
DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
91
DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
92
DMUB_SR(DMCUB_REGION6_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
93
DMUB_SR(DMCUB_REGION6_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
94
DMUB_SR(DMCUB_REGION6_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
95
DMUB_SR(DMCUB_SCRATCH0) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
96
DMUB_SR(DMCUB_SCRATCH1) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
97
DMUB_SR(DMCUB_SCRATCH2) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
98
DMUB_SR(DMCUB_SCRATCH3) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn35.h
99
DMUB_SR(DMCUB_SCRATCH4) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
100
DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
101
DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
102
DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
103
DMUB_SR(DMCUB_REGION3_TMR_AXI_SPACE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
104
DMUB_SR(DMCUB_INTERRUPT_ENABLE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
105
DMUB_SR(DMCUB_INTERRUPT_ACK) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
106
DMUB_SR(DMCUB_INTERRUPT_STATUS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
107
DMUB_SR(DMCUB_REG_INBOX0_RDY) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
108
DMUB_SR(DMCUB_REG_INBOX0_MSG0) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
109
DMUB_SR(DMCUB_REG_INBOX0_MSG1) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
110
DMUB_SR(DMCUB_REG_INBOX0_MSG2) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
111
DMUB_SR(DMCUB_REG_INBOX0_MSG3) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
112
DMUB_SR(DMCUB_REG_INBOX0_MSG4) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
113
DMUB_SR(DMCUB_REG_INBOX0_MSG5) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
114
DMUB_SR(DMCUB_REG_INBOX0_MSG6) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
115
DMUB_SR(DMCUB_REG_INBOX0_MSG7) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
116
DMUB_SR(DMCUB_REG_INBOX0_MSG8) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
117
DMUB_SR(DMCUB_REG_INBOX0_MSG9) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
118
DMUB_SR(DMCUB_REG_INBOX0_MSG10) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
119
DMUB_SR(DMCUB_REG_INBOX0_MSG11) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
120
DMUB_SR(DMCUB_REG_INBOX0_MSG12) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
121
DMUB_SR(DMCUB_REG_INBOX0_MSG13) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
122
DMUB_SR(DMCUB_REG_INBOX0_MSG14) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
123
DMUB_SR(DMCUB_REG_INBOX0_RSP) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
124
DMUB_SR(DMCUB_REG_OUTBOX0_RDY) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
125
DMUB_SR(DMCUB_REG_OUTBOX0_MSG0) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
126
DMUB_SR(DMCUB_REG_OUTBOX0_RSP) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
127
DMUB_SR(HOST_INTERRUPT_CSR)
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
15
DMUB_SR(DMCUB_CNTL) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
16
DMUB_SR(DMCUB_CNTL2) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
17
DMUB_SR(DMCUB_SEC_CNTL) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
18
DMUB_SR(DMCUB_INBOX0_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
19
DMUB_SR(DMCUB_INBOX0_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
20
DMUB_SR(DMCUB_INBOX0_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
21
DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
22
DMUB_SR(DMCUB_INBOX1_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
23
DMUB_SR(DMCUB_INBOX1_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
24
DMUB_SR(DMCUB_INBOX1_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
25
DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
26
DMUB_SR(DMCUB_OUTBOX0_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
27
DMUB_SR(DMCUB_OUTBOX0_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
28
DMUB_SR(DMCUB_OUTBOX0_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
29
DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
30
DMUB_SR(DMCUB_OUTBOX1_SIZE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
31
DMUB_SR(DMCUB_OUTBOX1_RPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
32
DMUB_SR(DMCUB_OUTBOX1_WPTR) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
33
DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
34
DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
35
DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
36
DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
37
DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
38
DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
39
DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
40
DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
41
DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
42
DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
43
DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
44
DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
45
DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
46
DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
47
DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
48
DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
49
DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
50
DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
51
DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
52
DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
53
DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
54
DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
55
DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
56
DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
57
DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
58
DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
59
DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
60
DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
61
DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
62
DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
63
DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
64
DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
65
DMUB_SR(DMCUB_REGION4_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
66
DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
67
DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
68
DMUB_SR(DMCUB_REGION5_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
69
DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
70
DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
71
DMUB_SR(DMCUB_REGION6_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
72
DMUB_SR(DMCUB_REGION6_OFFSET_HIGH) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
73
DMUB_SR(DMCUB_REGION6_TOP_ADDRESS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
74
DMUB_SR(DMCUB_SCRATCH0) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
75
DMUB_SR(DMCUB_SCRATCH1) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
76
DMUB_SR(DMCUB_SCRATCH2) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
77
DMUB_SR(DMCUB_SCRATCH3) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
78
DMUB_SR(DMCUB_SCRATCH4) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
79
DMUB_SR(DMCUB_SCRATCH5) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
80
DMUB_SR(DMCUB_SCRATCH6) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
81
DMUB_SR(DMCUB_SCRATCH7) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
82
DMUB_SR(DMCUB_SCRATCH8) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
83
DMUB_SR(DMCUB_SCRATCH9) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
84
DMUB_SR(DMCUB_SCRATCH10) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
85
DMUB_SR(DMCUB_SCRATCH11) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
86
DMUB_SR(DMCUB_SCRATCH12) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
87
DMUB_SR(DMCUB_SCRATCH13) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
88
DMUB_SR(DMCUB_SCRATCH14) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
89
DMUB_SR(DMCUB_SCRATCH15) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
90
DMUB_SR(DMCUB_SCRATCH16) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
91
DMUB_SR(DMCUB_SCRATCH17) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
92
DMUB_SR(DMCUB_GPINT_DATAIN0) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
93
DMUB_SR(DMCUB_GPINT_DATAIN1) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
94
DMUB_SR(DMCUB_GPINT_DATAOUT) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
95
DMUB_SR(CC_DC_PIPE_DIS) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
96
DMUB_SR(MMHUBBUB_SOFT_RESET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
97
DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
98
DMUB_SR(DCN_VM_FB_OFFSET) \
sys/dev/pci/drm/amd/display/dmub/src/dmub_dcn401.h
99
DMUB_SR(DMCUB_TIMER_CURRENT) \