DML_ASSERT
DML_ASSERT(cfg_support_info->stream_support_info[stream_index].odms_used <= 4);
DML_ASSERT(cfg_support_info->stream_support_info[stream_index].num_odm_output_segments == 4 ||
DML_ASSERT(cfg_support_info->stream_support_info[stream_index].num_odm_output_segments == 1);
DML_ASSERT(mode_lib->mp.Dppclk[k] > 0);
DML_ASSERT(mode_lib->mp.Dcfclk > 0);
DML_ASSERT(mode_lib->mp.FabricClock > 0);
DML_ASSERT(mode_lib->mp.dram_bw_mbps > 0);
DML_ASSERT(mode_lib->mp.uclk_freq_mhz > 0);
DML_ASSERT(mode_lib->mp.GlobalDPPCLK > 0);
DML_ASSERT(mode_lib->mp.Dispclk > 0);
DML_ASSERT(mode_lib->mp.DCFCLKDeepSleep > 0);
DML_ASSERT(s->SOCCLK > 0);
DML_ASSERT(0);
DML_ASSERT(mode_lib->mp.dcfclk_deep_sleep_hysteresis < 256);
DML_ASSERT(p0_pte_row_height_linear >= 8);
DML_ASSERT(p1_pte_row_height_linear >= 8);
DML_ASSERT(l->plane_idx < DML2_MAX_PLANES);
DML_ASSERT(l->refclk_freq_in_mhz != 0);
DML_ASSERT(l->pclk_freq_in_mhz != 0);
DML_ASSERT(l->ref_freq_to_pix_freq < 4.0);
DML_ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)math_pow(2, 13));
DML_ASSERT(l->dst_y_prefetch > (l->dst_y_per_vm_vblank + l->dst_y_per_row_vblank));
DML_ASSERT(display_cfg->plane_descriptors[l->plane_idx].cursor.num_cursors <= 1);
DML_ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)math_pow(2, 18));
DML_ASSERT(l->refcyc_per_req_delivery_pre_l < math_pow(2, 13));
DML_ASSERT(l->refcyc_per_req_delivery_l < math_pow(2, 13));
DML_ASSERT(l->refcyc_per_req_delivery_pre_c < math_pow(2, 13));
DML_ASSERT(l->refcyc_per_req_delivery_c < math_pow(2, 13));
DML_ASSERT(disp_dlg_regs->dst_y_after_scaler < (unsigned int)8);
DML_ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)math_pow(2, 13));
DML_ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)math_pow(2, 13));
DML_ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)math_pow(2, 13));
DML_ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)math_pow(2, 13));
DML_ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)math_pow(2, 13));
DML_ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)math_pow(2, 13));
DML_ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)math_pow(2, 13));
DML_ASSERT(disp_ttu_regs->qos_level_low_wm < (unsigned int)math_pow(2, 14));
DML_ASSERT(disp_ttu_regs->qos_level_high_wm < (unsigned int)math_pow(2, 14));
DML_ASSERT(disp_ttu_regs->min_ttu_vblank < (unsigned int)math_pow(2, 24));
DML_ASSERT(0);
DML_ASSERT(p->mcache_line_size_bytes != 0);
DML_ASSERT(p->mcache_size_bytes != 0);
DML_ASSERT(0);
DML_ASSERT(*p->num_mcaches > 0);
DML_ASSERT(*p->num_mcaches_l > 0);
DML_ASSERT(*p->num_mcaches_c > 0);
DML_ASSERT(0);
DML_ASSERT(VRatio > 0);
DML_ASSERT(0);
DML_ASSERT(0);
DML_ASSERT(0);
DML_ASSERT(*p->dst_y_prefetch < 64);
DML_ASSERT(max_idx >= 0);
DML_ASSERT(p->urg_bandwidth_required[m][n] >= p->non_urg_bandwidth_required[m][n]);
DML_ASSERT(0);
DML_ASSERT(urg_bandwidth_required_flip[eval_state][n] >= non_urg_bandwidth_required_flip[eval_state][n]);
DML_ASSERT(l->min_row_time > 0);
DML_ASSERT(clk_entry_found);
DML_ASSERT(0);
DML_ASSERT(0);
DML_ASSERT(0);
DML_ASSERT(0);
DML_ASSERT(0);
DML_ASSERT(clk_entry_found);
DML_ASSERT(0);
DML_ASSERT(base_strategy_list_1_display_size <= PMO_DCN4_MAX_BASE_STRATEGIES);
DML_ASSERT(base_strategy_list_2_display_size <= PMO_DCN4_MAX_BASE_STRATEGIES);
DML_ASSERT(base_strategy_list_3_display_size <= PMO_DCN4_MAX_BASE_STRATEGIES);
DML_ASSERT(base_strategy_list_4_display_size <= PMO_DCN4_MAX_BASE_STRATEGIES);
DML_ASSERT(condition); \