sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

385

memset(&context->bw_ctx.bw.dcn.fams2_stream_base_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

386

memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_utils.c

387

memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params_v2, 0, sizeof(union dmub_fams2_stream_static_sub_state_v2) * DML2_MAX_PLANES);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

113

for (dml_prog_idx = 0; dml_prog_idx < DML2_MAX_PLANES; dml_prog_idx++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h

440

struct dml2_plane_parameters plane_descriptors[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h

441

struct dml2_stream_parameters stream_descriptors[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

240

struct dml2_dchub_per_pipe_register_set *pipe_regs[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

246

struct dml2_dchub_per_pipe_register_set *pipe_regs[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

337

enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

347

bool MPCCombineEnable[DML2_MAX_PLANES]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

348

enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

349

unsigned int DPPPerSurface[DML2_MAX_PLANES]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4.

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

350

bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mode_programming

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

351

bool FECEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the FEC is actually required

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

352

unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// <brief Indicate how many slices needed to support the given mode

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

353

double OutputBpp[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

354

enum dml2_output_type_and_rate__type OutputType[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

355

enum dml2_output_type_and_rate__rate OutputRate[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

356

unsigned int AlignedYPitch[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

357

unsigned int AlignedCPitch[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

431

struct dml2_per_plane_programming plane_programming[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

432

struct dml2_per_stream_programming stream_programming[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

435

struct dml2_dchub_per_pipe_register_set pipe_regs[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

461

} plane_info[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

469

unsigned int subviewport_lines_needed_in_mall[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

575

unsigned long long det_size_in_kbytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

576

unsigned long long DETBufferSizeY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

589

} dcc_control[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

611

double min_ttu_vblank_us[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

612

bool vready_at_or_after_vsync[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

613

double min_dst_y_next_start[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

617

unsigned int dst_x_after_scaler[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

618

unsigned int dst_y_after_scaler[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

619

unsigned int prefetch_source_lines_plane0[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

620

unsigned int prefetch_source_lines_plane1[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

621

bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

622

bool UsesMALLForStaticScreen[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

623

unsigned int CursorDstXOffset[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

624

unsigned int CursorDstYOffset[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

625

unsigned int CursorChunkHDLAdjust[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

626

unsigned int dpte_group_bytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

627

unsigned int vm_group_bytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

628

double DisplayPipeRequestDeliveryTimeLuma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

629

double DisplayPipeRequestDeliveryTimeChroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

630

double DisplayPipeRequestDeliveryTimeLumaPrefetch[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

631

double DisplayPipeRequestDeliveryTimeChromaPrefetch[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

632

double TimePerVMGroupVBlank[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

633

double TimePerVMGroupFlip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

634

double TimePerVMRequestVBlank[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

635

double TimePerVMRequestFlip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

636

double Tdmdl_vm[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

637

double Tdmdl[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

638

unsigned int VStartup[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

639

unsigned int VUpdateOffsetPix[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

640

unsigned int VUpdateWidthPix[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

641

unsigned int VReadyOffsetPix[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

643

double DST_Y_PER_PTE_ROW_NOM_L[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

644

double DST_Y_PER_PTE_ROW_NOM_C[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

645

double time_per_pte_group_nom_luma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

646

double time_per_pte_group_nom_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

647

double time_per_pte_group_vblank_luma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

648

double time_per_pte_group_vblank_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

649

double time_per_pte_group_flip_luma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

650

double time_per_pte_group_flip_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

651

double VRatioPrefetchY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

652

double VRatioPrefetchC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

653

double DestinationLinesForPrefetch[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

654

double DestinationLinesToRequestVMInVBlank[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

655

double DestinationLinesToRequestRowInVBlank[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

656

double DestinationLinesToRequestVMInImmediateFlip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

657

double DestinationLinesToRequestRowInImmediateFlip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

658

double DisplayPipeLineDeliveryTimeLuma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

659

double DisplayPipeLineDeliveryTimeChroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

660

double DisplayPipeLineDeliveryTimeLumaPrefetch[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

661

double DisplayPipeLineDeliveryTimeChromaPrefetch[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

664

double WritebackAllowDRAMClockChangeEndPosition[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

665

double WritebackAllowFCLKChangeEndPosition[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

666

double DSCCLK_calculated[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

667

unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

668

bool PTE_BUFFER_MODE[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

669

double DSCDelay[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

670

double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

671

unsigned int PrefetchMode[DML2_MAX_PLANES]; // LEGACY_ONLY

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

682

struct dml2_mcache_surface_allocation non_optimized_mcache_allocation[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

715

struct dml2_plane_mcache_configuration_descriptor mcache_configurations[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

723

struct dml2_hubp_pipe_mcache_regs *per_plane_pipe_mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

198

memset(scratch->main_stream_index_from_svp_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

199

memset(scratch->svp_stream_index_from_main_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c

200

memset(scratch->main_plane_index_to_phantom_plane_index, 0, sizeof(int) * DML2_MAX_PLANES);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10249

memset(l->stream_visited, 0, DML2_MAX_PLANES * sizeof(bool));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

1028

bool DETPieceAssignedToThisSurfaceAlready[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12367

DML_ASSERT(l->plane_idx < DML2_MAX_PLANES);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12381

if (l->plane_idx < DML2_MAX_PLANES) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

12418

l->first_pipe_idx_in_plane = DML2_MAX_PLANES;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

221

for (unsigned int k = 0; k < DML2_MAX_PLANES; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

225

for (unsigned int plane_idx = 0; plane_idx < DML2_MAX_PLANES; plane_idx++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3515

double DCFClkDeepSleepPerSurface[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3604

double zero_double[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3605

unsigned int zero_integer[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3607

memset(zero_double, 0, DML2_MAX_PLANES * sizeof(double));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3608

memset(zero_integer, 0, DML2_MAX_PLANES * sizeof(unsigned int));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3693

unsigned int MaximumSwathHeightY[DML2_MAX_PLANES] = { 0 };

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3694

unsigned int MaximumSwathHeightC[DML2_MAX_PLANES] = { 0 };

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3695

unsigned int RoundedUpSwathSizeBytesY[DML2_MAX_PLANES] = { 0 };

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3696

unsigned int RoundedUpSwathSizeBytesC[DML2_MAX_PLANES] = { 0 };

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3697

unsigned int SwathWidthSingleDPP[DML2_MAX_PLANES] = { 0 };

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

3698

unsigned int SwathWidthSingleDPPChroma[DML2_MAX_PLANES] = { 0 };

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7004

double (*surface_avg_vactive_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7005

double (*surface_peak_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES],

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8598

memset(s->stream_visited, 0, DML2_MAX_PLANES * sizeof(bool));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8777

memset(s->stream_visited, 0, DML2_MAX_PLANES * sizeof(bool));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1000

unsigned int mcache_shift_granularity_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1002

unsigned int num_mcaches_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1003

unsigned int mcache_row_bytes_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1004

unsigned int mcache_row_bytes_per_channel_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1005

unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1006

unsigned int mcache_shift_granularity_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1008

bool mall_comb_mcache_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1009

bool mall_comb_mcache_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1010

bool lc_comb_mcache[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1012

double impacted_prefetch_margin_us[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1038

double PixelClockBackEnd[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1039

double OutputBpp[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1041

unsigned int meta_row_height_luma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1042

unsigned int meta_row_height_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1043

unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1044

unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1045

unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1046

unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1050

unsigned int dummy_integer_array[36][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1051

enum dml2_odm_mode dummy_odm_mode[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1052

bool dummy_boolean_array[2][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1054

double dummy_single_array[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1057

double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1059

unsigned int MaximumVStartup[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1060

unsigned int DSTYAfterScaler[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1061

unsigned int DSTXAfterScaler[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1064

struct dml2_core_internal_DmlPipe SurfParameters[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1100

double Tvm_trips[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1101

double Tr0_trips[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1102

double Tvm_trips_flip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1103

double Tr0_trips_flip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1104

double Tvm_trips_flip_rounded[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1105

double Tr0_trips_flip_rounded[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1106

unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1108

unsigned int vmpg_width_y[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1109

unsigned int vmpg_height_y[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1110

unsigned int vmpg_width_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1111

unsigned int vmpg_height_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1112

unsigned int full_swath_bytes_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1113

unsigned int full_swath_bytes_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1115

unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1116

unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1117

unsigned int tdlut_row_bytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1118

unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1119

double tdlut_opt_time[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1120

double tdlut_drain_time[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1121

unsigned int tdlut_bytes_to_deliver[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1122

unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1124

unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1125

unsigned int cursor_bytes_per_line[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1126

unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1127

unsigned int cursor_bytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1128

bool stream_visited[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1130

unsigned int pstate_bytes_required_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1131

unsigned int pstate_bytes_required_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1133

double prefetch_sw_bytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1134

double Tpre_rounded[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1135

double Tpre_oto[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1138

double impacted_dst_y_pre[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1139

double line_times[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1140

enum dml2_source_format_class pixel_format[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1141

unsigned int lb_source_lines_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1142

unsigned int lb_source_lines_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1143

double prefetch_swath_time_us[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1147

double PixelClockBackEnd[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1148

double OutputBpp[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1156

double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1157

double surface_dummy_bw0[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1158

unsigned int dummy_integer_array[4][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1159

enum dml2_output_encoder_class dummy_output_encoder_array[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1160

double dummy_single_array[2][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1161

unsigned int dummy_long_array[8][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1162

bool dummy_boolean_array[2][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1168

struct dml2_core_internal_DmlPipe SurfaceParameters[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1175

unsigned int MaxVStartupLines[DML2_MAX_PLANES]; /// <brief more like vblank for the plane's OTG

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1188

unsigned int vmpg_width_y[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1189

unsigned int vmpg_height_y[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1190

unsigned int vmpg_width_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1191

unsigned int vmpg_height_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1192

unsigned int full_swath_bytes_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1193

unsigned int full_swath_bytes_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1195

unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1196

unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1197

unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1198

unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1200

unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1201

unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1202

unsigned int tdlut_row_bytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1203

unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1204

double tdlut_opt_time[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1205

double tdlut_drain_time[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1206

unsigned int tdlut_bytes_to_deliver[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1207

unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1209

unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1210

unsigned int cursor_bytes_per_line[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1211

unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1212

unsigned int cursor_bytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1214

double Tvm_trips[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1215

double Tr0_trips[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1216

double Tvm_trips_flip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1217

double Tr0_trips_flip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1218

double Tvm_trips_flip_rounded[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1219

double Tr0_trips_flip_rounded[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1220

unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1222

unsigned int pstate_bytes_required_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1223

unsigned int pstate_bytes_required_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1225

double prefetch_sw_bytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1226

double Tpre_rounded[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1227

double Tpre_oto[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1229

double impacted_dst_y_pre[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1230

double line_times[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1231

enum dml2_source_format_class pixel_format[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1232

unsigned int lb_source_lines_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1233

unsigned int lb_source_lines_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1234

unsigned int num_dsc_slices[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1235

bool dsc_enable[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1239

double ActiveDRAMClockChangeLatencyMargin[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1240

double ActiveFCLKChangeLatencyMargin[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1241

double USRRetrainingLatencyMargin[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1242

double g6_temp_read_latency_margin[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1243

double temp_read_or_ppt_latency_margin[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1247

double LinesInDETY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1248

double LinesInDETC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1249

unsigned int LinesInDETYRoundedDownToSwath[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1250

unsigned int LinesInDETCRoundedDownToSwath[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1258

unsigned int LBLatencyHidingSourceLinesY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1259

unsigned int LBLatencyHidingSourceLinesC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1276

unsigned int PTEBufferSizeInRequestsForLuma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1277

unsigned int PTEBufferSizeInRequestsForChroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1280

unsigned int PixelPTEBytesPerRowY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1281

unsigned int PixelPTEBytesPerRowC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1282

unsigned int PixelPTEBytesPerRowStorageY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1283

unsigned int PixelPTEBytesPerRowStorageC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1284

unsigned int PixelPTEBytesPerRowY_one_row_per_frame[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1285

unsigned int PixelPTEBytesPerRowC_one_row_per_frame[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1286

unsigned int dpte_row_width_luma_ub_one_row_per_frame[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1287

unsigned int dpte_row_height_luma_one_row_per_frame[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1288

unsigned int dpte_row_width_chroma_ub_one_row_per_frame[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1289

unsigned int dpte_row_height_chroma_one_row_per_frame[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1290

bool one_row_per_frame_fits_in_buffer[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1292

unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1293

unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1309

enum dml2_pstate_method pstate_switch_modes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1497

unsigned int MaximumSwathHeightY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1498

unsigned int MaximumSwathHeightC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1499

unsigned int RoundedUpSwathSizeBytesY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1500

unsigned int RoundedUpSwathSizeBytesC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1501

unsigned int SwathWidthSingleDPP[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1502

unsigned int SwathWidthSingleDPPChroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1503

unsigned int SwathTimeValueUs[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1520

unsigned int TotalBandwidthPerStream[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1522

unsigned int DETBudgetPerStream[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1523

unsigned int RemainingDETBudgetPerStream[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1537

double per_plane_flip_bw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1551

double unity_array[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1552

double zero_array[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1553

double surface_dummy_bw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1783

unsigned int dummy[2][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1784

unsigned int swath_width_luma_ub_single_dpp[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1785

unsigned int swath_width_chroma_ub_single_dpp[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1842

bool stream_visited[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

2025

unsigned int accumulated_return_path_dcfclk_cycles[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

2027

unsigned int src_swath_bytes_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

2028

unsigned int src_swath_bytes_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

2029

unsigned int src_detile_buf_size_bytes_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

2030

unsigned int src_detile_buf_size_bytes_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

2188

double (*surface_avg_vactive_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

2189

double (*surface_peak_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

260

enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

261

enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

279

bool MPCCombineEnable[DML2_MAX_PLANES]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

280

enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

281

unsigned int DPPPerSurface[DML2_MAX_PLANES]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4.

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

282

bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mode_programming

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

283

bool FECEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the FEC is actually required

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

284

unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// <brief Indicate how many slices needed to support the given mode

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

286

double OutputBpp[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

287

enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

288

enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

290

unsigned int AlignedYPitch[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

291

unsigned int AlignedCPitch[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

293

unsigned int AlignedDCCMetaPitchY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

294

unsigned int AlignedDCCMetaPitchC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

296

unsigned int request_size_bytes_luma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

297

unsigned int request_size_bytes_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

298

enum dml2_core_internal_request_type RequestLuma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

299

enum dml2_core_internal_request_type RequestChroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

301

unsigned int DCCYMaxUncompressedBlock[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

302

unsigned int DCCYMaxCompressedBlock[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

303

unsigned int DCCYIndependentBlock[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

304

unsigned int DCCCMaxUncompressedBlock[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

305

unsigned int DCCCMaxCompressedBlock[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

306

unsigned int DCCCIndependentBlock[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

350

double RequiredDPPCLK[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

351

double RequiredDISPCLKPerSurface[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

352

double RequiredDTBCLK[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

354

double required_dscclk_freq_mhz[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

372

bool NoTimeForPrefetch[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

373

bool NoTimeForDynamicMetadata[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

388

unsigned int DETBufferSizeInKByte[DML2_MAX_PLANES]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value.

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

389

unsigned int DETBufferSizeY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

390

unsigned int DETBufferSizeC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

391

unsigned int SwathHeightY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

392

unsigned int SwathHeightC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

393

unsigned int SwathWidthY[DML2_MAX_PLANES]; // per-pipe

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

394

unsigned int SwathWidthC[DML2_MAX_PLANES]; // per-pipe

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

403

double TWait[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

409

double VRatioPreY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

410

double VRatioPreC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

411

unsigned int req_per_swath_ub_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

412

unsigned int req_per_swath_ub_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

413

unsigned int swath_width_luma_ub[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

414

unsigned int swath_width_chroma_ub[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

415

unsigned int RequiredSlots[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

416

unsigned int vm_bytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

417

unsigned int DPTEBytesPerRow[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

418

unsigned int PrefetchLinesY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

419

unsigned int PrefetchLinesC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

420

unsigned int MaxNumSwathY[DML2_MAX_PLANES]; /// <brief Max number of swath for prefetch

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

421

unsigned int MaxNumSwathC[DML2_MAX_PLANES]; /// <brief Max number of swath for prefetch

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

422

unsigned int PrefillY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

423

unsigned int PrefillC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

424

unsigned int full_swath_bytes_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

425

unsigned int full_swath_bytes_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

427

bool use_one_row_for_frame[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

428

bool use_one_row_for_frame_flip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

430

double dst_y_prefetch[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

431

double LinesForVM[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

432

double LinesForDPTERow[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

433

unsigned int SwathWidthYSingleDPP[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

434

unsigned int SwathWidthCSingleDPP[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

435

unsigned int BytePerPixelY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

436

unsigned int BytePerPixelC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

437

double BytePerPixelInDETY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

438

double BytePerPixelInDETC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

440

unsigned int Read256BlockHeightY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

441

unsigned int Read256BlockWidthY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

442

unsigned int Read256BlockHeightC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

443

unsigned int Read256BlockWidthC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

444

unsigned int MacroTileHeightY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

445

unsigned int MacroTileHeightC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

446

unsigned int MacroTileWidthY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

447

unsigned int MacroTileWidthC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

449

bool surf_linear128_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

450

bool surf_linear128_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

452

double PSCL_FACTOR[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

453

double PSCL_FACTOR_CHROMA[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

454

double MaximumSwathWidthLuma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

455

double MaximumSwathWidthChroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

456

double Tno_bw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

457

double Tno_bw_flip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

458

double dst_y_per_vm_flip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

459

double dst_y_per_row_flip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

460

double WritebackDelayTime[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

461

unsigned int dpte_group_bytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

462

unsigned int dpte_row_height[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

463

unsigned int dpte_row_height_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

466

double UrgentBurstFactorCursor[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

467

double UrgentBurstFactorCursorPre[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

468

double UrgentBurstFactorLuma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

469

double UrgentBurstFactorLumaPre[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

470

double UrgentBurstFactorChroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

471

double UrgentBurstFactorChromaPre[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

478

double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES]; // overhead to request meta

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

479

double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

480

double dcc_dram_bw_pref_overhead_factor_p0[DML2_MAX_PLANES]; // overhead to request meta

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

481

double dcc_dram_bw_pref_overhead_factor_p1[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

482

double mall_prefetch_sdp_overhead_factor[DML2_MAX_PLANES]; // overhead to the imall or phantom pipe

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

483

double mall_prefetch_dram_overhead_factor[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

485

bool is_using_mall_for_ss[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

486

unsigned int meta_row_width_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

487

unsigned int PixelPTEReqHeightC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

488

bool PTE_BUFFER_MODE[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

489

unsigned int meta_req_height_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

490

unsigned int meta_pte_bytes_per_frame_ub_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

491

unsigned int dpde0_bytes_per_frame_ub_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

492

unsigned int dpte_row_width_luma_ub[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

493

unsigned int meta_req_width[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

494

unsigned int meta_row_width[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

495

unsigned int PixelPTEReqWidthY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

496

unsigned int dpte_row_height_linear[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

497

unsigned int PTERequestSizeY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

498

unsigned int dpte_row_width_chroma_ub[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

499

unsigned int PixelPTEReqWidthC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

500

unsigned int meta_pte_bytes_per_frame_ub_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

501

unsigned int dpte_row_height_linear_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

502

unsigned int PTERequestSizeC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

503

unsigned int meta_req_height[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

504

unsigned int dpde0_bytes_per_frame_ub_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

505

unsigned int meta_req_width_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

506

unsigned int PixelPTEReqHeightY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

507

unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

508

unsigned int vm_group_bytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

509

unsigned int VReadyOffsetPix[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

510

unsigned int VUpdateOffsetPix[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

511

unsigned int VUpdateWidthPix[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

512

double TSetup[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

513

double Tdmdl_vm_raw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

514

double Tdmdl_raw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

515

unsigned int VStartupMin[DML2_MAX_PLANES]; /// <brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos.

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

516

double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

520

bool RequiresDSC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

521

bool RequiresFEC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

522

double OutputBpp[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

523

double DesiredOutputBpp[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

524

double PixelClockBackEnd[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

525

unsigned int DSCDelay[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

526

enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

527

enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

536

unsigned int EstimatedNumberOfDSCSlices[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

540

double vactive_sw_bw_l[DML2_MAX_PLANES]; // no dcc overhead, for the plane

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

541

double vactive_sw_bw_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

542

double WriteBandwidth[DML2_MAX_PLANES][DML2_MAX_WRITEBACK];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

543

double RequiredPrefetchPixelDataBWLuma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

544

double RequiredPrefetchPixelDataBWChroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

552

double RequiredPrefetchBWMax[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

553

double cursor_bw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

554

double prefetch_cursor_bw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

555

double prefetch_vmrow_bw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

556

double final_flip_bw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

557

double meta_row_bw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

558

unsigned int meta_row_bytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

559

double dpte_row_bw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

560

double excess_vactive_fill_bw_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

561

double excess_vactive_fill_bw_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

562

double surface_avg_vactive_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

563

double surface_peak_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

566

enum dml2_odm_mode ODMMode[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

567

unsigned int SurfaceSizeInMALL[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

568

unsigned int NoOfDPP[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

569

bool MPCCombine[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

571

double MinDPPCLKUsingSingleDPP[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

572

bool SingleDPPViewportSizeSupportPerSurface[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

573

bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

574

bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

575

bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

576

bool PTEBufferSizeNotExceeded[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

577

bool DCCMetaBufferSizeNotExceeded[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

583

unsigned int SubViewportLinesNeededInMALL[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

584

double VActiveLatencyHidingMargin[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

585

double VActiveLatencyHidingUs[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

586

unsigned int MaxVStartupLines[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

587

double dram_change_vactive_det_fill_delay_us[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

589

unsigned int num_mcaches_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

590

unsigned int mcache_row_bytes_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

591

unsigned int mcache_row_bytes_per_channel_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

592

unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

593

unsigned int mcache_shift_granularity_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

595

unsigned int num_mcaches_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

596

unsigned int mcache_row_bytes_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

597

unsigned int mcache_row_bytes_per_channel_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

598

unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

599

unsigned int mcache_shift_granularity_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

601

bool mall_comb_mcache_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

602

bool mall_comb_mcache_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

603

bool lc_comb_mcache[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

605

unsigned int vmpg_width_y[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

606

unsigned int vmpg_height_y[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

607

unsigned int vmpg_width_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

608

unsigned int vmpg_height_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

610

unsigned int meta_row_height_luma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

611

unsigned int meta_row_height_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

612

unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

613

unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

614

unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

615

unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

617

unsigned int pstate_bytes_required_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

618

unsigned int pstate_bytes_required_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

619

unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

620

unsigned int cursor_bytes_per_line[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

622

unsigned int MaximumVStartup[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

627

unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

628

unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

629

unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

630

double tdlut_opt_time[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

631

double tdlut_drain_time[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

632

unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

634

double Tvm_trips_flip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

635

double Tr0_trips_flip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

636

double Tvm_trips_flip_rounded[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

637

double Tr0_trips_flip_rounded[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

639

unsigned int DSTYAfterScaler[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

640

unsigned int DSTXAfterScaler[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

642

enum dml2_pstate_method pstate_switch_modes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

654

unsigned int NoOfDPP[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

655

enum dml2_odm_mode ODMMode[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

663

unsigned int VInitPreFillY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

664

unsigned int VInitPreFillC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

665

unsigned int MaxNumSwathY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

666

unsigned int MaxNumSwathC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

667

unsigned int full_swath_bytes_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

668

unsigned int full_swath_bytes_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

670

double BytePerPixelInDETY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

671

double BytePerPixelInDETC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

672

unsigned int BytePerPixelY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

673

unsigned int BytePerPixelC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

674

unsigned int SwathWidthY[DML2_MAX_PLANES]; // per-pipe

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

675

unsigned int SwathWidthC[DML2_MAX_PLANES]; // per-pipe

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

676

unsigned int req_per_swath_ub_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

677

unsigned int req_per_swath_ub_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

678

unsigned int SwathWidthSingleDPPY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

679

unsigned int SwathWidthSingleDPPC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

680

double vactive_sw_bw_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

681

double vactive_sw_bw_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

682

double excess_vactive_fill_bw_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

683

double excess_vactive_fill_bw_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

685

unsigned int PixelPTEBytesPerRow[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

686

unsigned int vm_bytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

687

unsigned int PrefetchSourceLinesY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

688

double RequiredPrefetchPixelDataBWLuma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

689

double RequiredPrefetchPixelDataBWChroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

690

unsigned int PrefetchSourceLinesC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

691

double PSCL_THROUGHPUT[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

692

double PSCL_THROUGHPUT_CHROMA[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

693

unsigned int DSCDelay[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

694

double DPPCLKUsingSingleDPP[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

696

unsigned int Read256BlockHeightY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

697

unsigned int Read256BlockWidthY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

698

unsigned int Read256BlockHeightC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

699

unsigned int Read256BlockWidthC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

700

unsigned int MacroTileHeightY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

701

unsigned int MacroTileHeightC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

702

unsigned int MacroTileWidthY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

703

unsigned int MacroTileWidthC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

704

double MaximumSwathWidthLuma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

705

double MaximumSwathWidthChroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

707

bool surf_linear128_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

708

bool surf_linear128_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

710

unsigned int SurfaceSizeInTheMALL[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

711

double VRatioPrefetchY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

712

double VRatioPrefetchC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

713

double Tno_bw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

714

double Tno_bw_flip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

715

double final_flip_bw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

716

double prefetch_vmrow_bw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

717

double cursor_bw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

718

double prefetch_cursor_bw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

719

double WritebackDelay[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

720

unsigned int dpte_row_height[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

721

unsigned int dpte_row_height_linear[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

722

unsigned int dpte_row_width_luma_ub[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

723

unsigned int dpte_row_width_chroma_ub[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

724

unsigned int dpte_row_height_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

725

unsigned int dpte_row_height_linear_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

726

unsigned int vm_group_bytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

727

unsigned int dpte_group_bytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

729

double dpte_row_bw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

730

double time_per_tdlut_group[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

731

double UrgentBurstFactorCursor[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

732

double UrgentBurstFactorCursorPre[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

733

double UrgentBurstFactorLuma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

734

double UrgentBurstFactorLumaPre[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

735

double UrgentBurstFactorChroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

736

double UrgentBurstFactorChromaPre[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

741

unsigned int vmpg_width_y[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

742

unsigned int vmpg_height_y[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

743

unsigned int vmpg_width_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

744

unsigned int vmpg_height_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

746

double meta_row_bw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

747

unsigned int meta_row_bytes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

748

unsigned int meta_req_width[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

749

unsigned int meta_req_height[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

750

unsigned int meta_row_width[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

751

unsigned int meta_row_height[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

752

unsigned int meta_req_width_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

753

unsigned int meta_row_height_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

754

unsigned int meta_row_width_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

755

unsigned int meta_req_height_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

757

unsigned int swath_width_luma_ub[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

758

unsigned int swath_width_chroma_ub[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

759

unsigned int PixelPTEReqWidthY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

760

unsigned int PixelPTEReqHeightY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

761

unsigned int PTERequestSizeY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

762

unsigned int PixelPTEReqWidthC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

763

unsigned int PixelPTEReqHeightC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

764

unsigned int PTERequestSizeC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

766

double TWait[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

767

double Tdmdl_vm_raw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

768

double Tdmdl_vm[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

769

double Tdmdl_raw[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

770

double Tdmdl[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

771

double TSetup[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

772

unsigned int dpde0_bytes_per_frame_ub_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

773

unsigned int dpde0_bytes_per_frame_ub_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

775

unsigned int meta_pte_bytes_per_frame_ub_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

776

unsigned int meta_pte_bytes_per_frame_ub_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

785

bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

786

bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

793

bool NotEnoughTimeForDynamicMetadata[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

795

bool use_one_row_for_frame[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

796

bool use_one_row_for_frame_flip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

804

double PixelClockBackEnd[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

805

double OutputBpp[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

806

bool dsc_enable[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

807

unsigned int num_dsc_slices[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

808

unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

809

unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

810

unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

811

unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

812

unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

813

unsigned int cursor_bytes_per_line[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

814

unsigned int MaxVStartupLines[DML2_MAX_PLANES]; /// <brief more like vblank for the plane's OTG

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

817

unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

818

unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

819

unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

820

double tdlut_opt_time[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

821

double tdlut_drain_time[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

822

unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

823

double Tvm_trips_flip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

824

double Tr0_trips_flip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

825

double Tvm_trips_flip_rounded[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

826

double Tr0_trips_flip_rounded[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

836

unsigned int pipe_plane[DML2_MAX_PLANES]; // <brief used mainly by dv to map the pipe inst to plane index within DML core; the plane idx of a pipe

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

839

bool NoTimeToPrefetch[DML2_MAX_PLANES]; // <brief Prefetch schedule calculation result

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

847

bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

853

double Dppclk[DML2_MAX_PLANES]; // <brief dppclk being used in mode programming

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

856

double DSCCLK[DML2_MAX_PLANES]; //< brief Required DSCCLK freq. Backend; not used in any subsequent calculations for now

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

864

unsigned int request_size_bytes_luma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

865

unsigned int request_size_bytes_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

866

enum dml2_core_internal_request_type RequestLuma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

867

enum dml2_core_internal_request_type RequestChroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

868

unsigned int DCCYMaxUncompressedBlock[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

869

unsigned int DCCYMaxCompressedBlock[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

870

unsigned int DCCYIndependentBlock[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

871

unsigned int DCCCMaxUncompressedBlock[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

872

unsigned int DCCCMaxCompressedBlock[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

873

unsigned int DCCCIndependentBlock[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

892

double MIN_DST_Y_NEXT_START[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

893

bool VREADY_AT_OR_AFTER_VSYNC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

894

unsigned int DSTYAfterScaler[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

895

unsigned int DSTXAfterScaler[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

896

double dst_y_prefetch[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

897

double dst_y_per_vm_vblank[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

898

double dst_y_per_row_vblank[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

899

double dst_y_per_vm_flip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

900

double dst_y_per_row_flip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

901

double MinTTUVBlank[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

902

double DisplayPipeLineDeliveryTimeLuma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

903

double DisplayPipeLineDeliveryTimeChroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

904

double DisplayPipeLineDeliveryTimeLumaPrefetch[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

905

double DisplayPipeLineDeliveryTimeChromaPrefetch[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

906

double DisplayPipeRequestDeliveryTimeLuma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

907

double DisplayPipeRequestDeliveryTimeChroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

908

double DisplayPipeRequestDeliveryTimeLumaPrefetch[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

909

double DisplayPipeRequestDeliveryTimeChromaPrefetch[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

910

unsigned int CursorDstXOffset[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

911

unsigned int CursorDstYOffset[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

912

unsigned int CursorChunkHDLAdjust[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

914

double DST_Y_PER_PTE_ROW_NOM_L[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

915

double DST_Y_PER_PTE_ROW_NOM_C[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

916

double time_per_pte_group_nom_luma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

917

double time_per_pte_group_nom_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

918

double time_per_pte_group_vblank_luma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

919

double time_per_pte_group_vblank_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

920

double time_per_pte_group_flip_luma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

921

double time_per_pte_group_flip_chroma[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

922

double TimePerVMGroupVBlank[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

923

double TimePerVMGroupFlip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

924

double TimePerVMRequestVBlank[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

925

double TimePerVMRequestFlip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

927

double DST_Y_PER_META_ROW_NOM_L[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

928

double DST_Y_PER_META_ROW_NOM_C[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

929

double TimePerMetaChunkNominal[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

930

double TimePerChromaMetaChunkNominal[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

931

double TimePerMetaChunkVBlank[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

932

double TimePerChromaMetaChunkVBlank[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

933

double TimePerMetaChunkFlip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

934

double TimePerChromaMetaChunkFlip[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

941

bool PTE_BUFFER_MODE[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

942

unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

943

double VActiveLatencyHidingUs[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

944

unsigned int SubViewportLinesNeededInMALL[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

945

bool is_using_mall_for_ss[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

948

unsigned int VStartupMin[DML2_MAX_PLANES]; /// <brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos.

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

949

unsigned int VStartup[DML2_MAX_PLANES]; /// <brief The vstartup value for OTG programming (will set to max vstartup; but now bounded by min(vblank_nom. actual vblank))

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

950

unsigned int VUpdateOffsetPix[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

951

unsigned int VUpdateWidthPix[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

952

unsigned int VReadyOffsetPix[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

953

unsigned int pstate_keepout_dst_lines[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

960

enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

961

enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

964

double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

965

double WritebackAllowFCLKChangeEndPosition[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

966

double WritebackAllowDRAMClockChangeEndPosition[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

969

unsigned int DETBufferSizeInKByte[DML2_MAX_PLANES]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value.

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

970

unsigned int DETBufferSizeY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

971

unsigned int DETBufferSizeC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

972

unsigned int SwathHeightY[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

973

unsigned int SwathHeightC[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

989

double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

990

double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

991

double dcc_dram_bw_pref_overhead_factor_p0[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

992

double dcc_dram_bw_pref_overhead_factor_p1[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

993

double mall_prefetch_sdp_overhead_factor[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

994

double mall_prefetch_dram_overhead_factor[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

996

unsigned int num_mcaches_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

997

unsigned int mcache_row_bytes_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

998

unsigned int mcache_row_bytes_per_channel_l[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

999

unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

403

for (unsigned int k = 0; k < DML2_MAX_PLANES; ++k) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

407

for (unsigned int plane_idx = 0; plane_idx < DML2_MAX_PLANES; plane_idx++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

617

memset(scratch->main_stream_index_from_svp_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

618

memset(scratch->svp_stream_index_from_main_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c

619

memset(scratch->main_plane_index_to_phantom_plane_index, 0, sizeof(int) * DML2_MAX_PLANES);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

420

unsigned int remap_array[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c

458

unsigned int remap_array[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c

202

unsigned int remap_array[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1043

for (i = 0; i < DML2_MAX_PLANES; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1088

unsigned int num_planes_per_stream[DML2_MAX_PLANES] = { 0 };

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1124

for (i = 0; i < DML2_MAX_PLANES; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1223

for (i = 0; i < DML2_MAX_PLANES; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1358

memset(s->pmo_dcn4.sorted_group_gtl_disallow_index, 0, sizeof(unsigned int) * DML2_MAX_PLANES);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1639

for (i = 0; i < DML2_MAX_PLANES; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

1654

for (i = 0; i < DML2_MAX_PLANES; i++) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

2149

sizeof(struct dml2_fams2_meta) * DML2_MAX_PLANES);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

550

enum dml2_pstate_method per_stream_variant_method[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

1025

memset(params->per_plane_pipe_mcache_regs, 0, DML2_MAX_PLANES * DML2_MAX_DCN_PIPES * sizeof(struct dml2_hubp_pipe_mcache_regs *));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_soc15.c

85

memcpy(params->display_config->stage2.per_plane_mcache_support, l->test_mcache.validate_admissibility_params.per_plane_status, sizeof(bool) * DML2_MAX_PLANES);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

176

struct core_stream_support_info stream_support_info[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

177

struct core_plane_support_info plane_support_info[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

218

} per_stream[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

224

} per_plane[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

243

bool per_plane_mcache_support[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

244

struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

315

enum dml2_pstate_method pstate_switch_modes[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

318

struct dml2_implicit_svp_meta stream_svp_meta[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

322

struct dml2_fams2_meta stream_fams2_meta[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

363

enum dml2_pstate_method per_stream_pstate_method[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

468

int main_stream_index_from_svp_stream_index[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

469

int svp_stream_index_from_main_stream_index[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

470

int main_plane_index_to_phantom_plane_index[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

471

int phantom_plane_index_to_main_plane_index[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

625

double reserved_time_candidates[DML2_MAX_PLANES][DML2_PMO_LEGACY_PREFETCH_MAX_TWAIT_OPTIONS];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

626

int reserved_time_candidates_count[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

627

int current_candidate[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

640

unsigned int stream_plane_mask[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

650

struct dml2_implicit_svp_meta stream_svp_meta[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

651

struct dml2_fams2_meta stream_fams2_meta[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

660

unsigned int synchronized_timing_group_masks[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

661

bool group_is_drr_enabled[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

662

bool group_is_drr_active[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

663

double group_line_time_us[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

666

struct dml2_fams2_per_method_common_meta group_common_fams2_meta[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

667

unsigned int sorted_group_gtl_disallow_index[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

668

unsigned int sorted_group_gtl_period_index[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

669

double group_phase_offset[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

748

bool per_plane_status[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

762

int per_pipe_viewport_x_start[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

763

int per_pipe_viewport_x_end[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

764

int pipe_count_per_plane[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

766

struct dml2_display_mcache_regs *current_mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; //One set per pipe/hubp

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

771

struct dml2_display_mcache_regs mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; //One set per pipe/hubp

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

926

struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

570

struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

572

union dmub_cmd_fams2_config fams2_stream_base_params[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

574

union dmub_cmd_fams2_config fams2_stream_sub_params[DML2_MAX_PLANES];

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

575

union dmub_fams2_stream_static_sub_state_v2 fams2_stream_sub_params_v2[DML2_MAX_PLANES];