sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

195

sizeof(int) * (DML2_MAX_MCACHES + 1));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c

198

sizeof(int) * (DML2_MAX_MCACHES + 1));

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h

132

int mcache_x_offsets_plane0[DML2_MAX_MCACHES + 1];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.h

133

int mcache_x_offsets_plane1[DML2_MAX_MCACHES + 1];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

150

int mcache_x_offsets_plane0[DML2_MAX_MCACHES + 1];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

151

int mcache_x_offsets_plane1[DML2_MAX_MCACHES + 1];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

166

int global_mcache_ids_plane0[DML2_MAX_MCACHES + 1];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

167

int global_mcache_ids_plane1[DML2_MAX_MCACHES + 1];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

168

int global_mcache_ids_mall_plane0[DML2_MAX_MCACHES + 1];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h

169

int global_mcache_ids_mall_plane1[DML2_MAX_MCACHES + 1];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

1005

unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

592

unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

598

unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h

999

unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1];