Symbol: DIV_ROUND_UP_ULL
sys/dev/pci/drm/amd/amdgpu/amdgpu_ttm.c
2416
num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes);
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
2479
DIV_ROUND_UP_ULL(exclusion_ranges[i].end, HZ_PER_MHZ);
sys/dev/pci/drm/display/drm_dp_helper.c
4593
return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
sys/dev/pci/drm/drm_fourcc.c
519
return DIV_ROUND_UP_ULL((u64)buffer_width * info->char_per_block[plane],
sys/dev/pci/drm/drm_rect.c
72
return DIV_ROUND_UP_ULL(tmp, dst);
sys/dev/pci/drm/i915/display/i9xx_wm.c
491
ret = DIV_ROUND_UP_ULL(ret, 10000);
sys/dev/pci/drm/i915/display/intel_bw.c
879
return DIV_ROUND_UP_ULL(mul_u32_u32(data_rate, 10), 512);
sys/dev/pci/drm/i915/display/intel_crtc.c
488
return DIV_ROUND_UP_ULL(mul_u32_u32(usecs, adjusted_mode->crtc_clock),
sys/dev/pci/drm/i915/display/intel_crtc.c
499
return DIV_ROUND_UP_ULL(mul_u32_u32(scanlines, adjusted_mode->crtc_htotal * 1000),
sys/dev/pci/drm/i915/display/intel_display.c
4053
return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10),
sys/dev/pci/drm/i915/display/intel_dp.c
456
return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),
sys/dev/pci/drm/i915/display/intel_dp_mst.c
220
m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);
sys/dev/pci/drm/i915/display/intel_dpll_mgr.c
3105
ssc_steplen = DIV_ROUND_UP_ULL(tmp, 32 * 2 * 32);
sys/dev/pci/drm/i915/display/intel_dpt.c
257
size = DIV_ROUND_UP_ULL(obj->size, I915_GTT_PAGE_SIZE);
sys/dev/pci/drm/i915/display/intel_fixed.h
102
tmp = DIV_ROUND_UP_ULL(tmp, d);
sys/dev/pci/drm/i915/display/intel_fixed.h
112
tmp = DIV_ROUND_UP_ULL(tmp, d.val);
sys/dev/pci/drm/i915/display/intel_fixed.h
80
tmp = DIV_ROUND_UP_ULL(tmp, 1 << 16);
sys/dev/pci/drm/i915/display/intel_plane.c
217
return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h),
sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c
122
scaled_vco_div_refclk2 = DIV_ROUND_UP_ULL(vco_div_refclk_float, 1000000);
sys/dev/pci/drm/i915/display/intel_sprite.c
592
return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, num * src_w),
sys/dev/pci/drm/i915/display/intel_sprite.c
955
return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, 10 * hscale),
sys/dev/pci/drm/i915/display/intel_vrr.c
222
vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
sys/dev/pci/drm/i915/display/skl_watermark.c
2203
dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale_k * vscale_k,
sys/dev/pci/drm/i915/display/skl_watermark.c
2234
latency = DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k *
sys/dev/pci/drm/i915/gt/intel_rc6.c
849
return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, id), 1000);
sys/dev/pci/drm/i915/i915_hwmon.c
703
*val = DIV_ROUND_UP_ULL(rotations * (MSEC_PER_SEC * 60), time);
sys/dev/pci/drm/i915/i915_scatterlist.c
100
if (WARN_ON(overflows_type(DIV_ROUND_UP_ULL(node->size, segment_pages),
sys/dev/pci/drm/i915/i915_scatterlist.c
106
if (sg_alloc_table(st, DIV_ROUND_UP_ULL(node->size, segment_pages),