sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c

2477

DIV_ROUND_DOWN_ULL(exclusion_ranges[i].start, HZ_PER_MHZ);

sys/dev/pci/drm/display/drm_dp_helper.c

4652

return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate * 10 * max_lanes,

sys/dev/pci/drm/display/drm_dp_mst_topology.c

3610

ret.full = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_rate * link_lane_count,

sys/dev/pci/drm/drm_rect.c

74

return DIV_ROUND_DOWN_ULL(tmp, dst);

sys/dev/pci/drm/drm_vblank.c

1019

vblank_start = DIV_ROUND_DOWN_ULL(

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

102

DIV_ROUND_DOWN_ULL(scaled_vco_div_refclk1, (curve_0_interpolated *

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

103

DIV_ROUND_DOWN_ULL(curve_1_interpolated, CURVE0_MULTIPLIER)));

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

106

DIV64_U64_ROUND_CLOSEST(DIV_ROUND_DOWN_ULL(adjusted_vco_clk1, curve_2_scaled1),

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

114

(curve_2_scaled_int * DIV_ROUND_DOWN_ULL(curve_0_interpolated,

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

119

DIV_ROUND_DOWN_ULL(1000000000000ULL, 55));

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

175

vco_div_refclk_integer = DIV_ROUND_DOWN_ULL(vco_clk, refclk_postscalar);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

177

vco_div_refclk_fracn = DIV_ROUND_DOWN_ULL(vco_clk_do_div << 32, refclk_postscalar);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

76

vco_div_refclk_float = vco_clk * DIV_ROUND_DOWN_ULL(1000000000000ULL, refclk_postscalar);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

88

curve_1_interpolated = DIV_ROUND_DOWN_ULL(curve_1_interpolated, CURVE1_MULTIPLIER);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

95

curve_2_scaled1 = DIV_ROUND_DOWN_ULL(temp, 16000);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

96

curve_2_scaled2 = DIV_ROUND_DOWN_ULL(temp, 160);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

99

scaled_vco_div_refclk1 = 112008301 * DIV_ROUND_DOWN_ULL(vco_div_refclk_float, 100000);