Symbol: DIVIL_MSR_BASE
sys/dev/pci/glxreg.h
192
#define DIVIL_GLD_MSR_CAP (DIVIL_MSR_BASE + 0x00)
sys/dev/pci/glxreg.h
193
#define DIVIL_GLD_MSR_CONFIG (DIVIL_MSR_BASE + 0x01)
sys/dev/pci/glxreg.h
194
#define DIVIL_GLD_MSR_SMI (DIVIL_MSR_BASE + 0x02)
sys/dev/pci/glxreg.h
195
#define DIVIL_GLD_MSR_ERROR (DIVIL_MSR_BASE + 0x03)
sys/dev/pci/glxreg.h
196
#define DIVIL_GLD_MSR_PM (DIVIL_MSR_BASE + 0x04)
sys/dev/pci/glxreg.h
197
#define DIVIL_GLD_MSR_DIAG (DIVIL_MSR_BASE + 0x05)
sys/dev/pci/glxreg.h
199
#define DIVIL_LBAR_IRQ (DIVIL_MSR_BASE + 0x08)
sys/dev/pci/glxreg.h
200
#define DIVIL_LBAR_KEL (DIVIL_MSR_BASE + 0x09)
sys/dev/pci/glxreg.h
201
#define DIVIL_LBAR_SMB (DIVIL_MSR_BASE + 0x0b)
sys/dev/pci/glxreg.h
202
#define DIVIL_LBAR_GPIO (DIVIL_MSR_BASE + 0x0c)
sys/dev/pci/glxreg.h
203
#define DIVIL_LBAR_MFGPT (DIVIL_MSR_BASE + 0x0d)
sys/dev/pci/glxreg.h
204
#define DIVIL_LBAR_ACPI (DIVIL_MSR_BASE + 0x0e)
sys/dev/pci/glxreg.h
205
#define DIVIL_LBAR_PMS (DIVIL_MSR_BASE + 0x0f)
sys/dev/pci/glxreg.h
206
#define DIVIL_LBAR_FLSH0 (DIVIL_MSR_BASE + 0x10)
sys/dev/pci/glxreg.h
207
#define DIVIL_LBAR_FLSH1 (DIVIL_MSR_BASE + 0x11)
sys/dev/pci/glxreg.h
208
#define DIVIL_LBAR_FLSH2 (DIVIL_MSR_BASE + 0x12)
sys/dev/pci/glxreg.h
209
#define DIVIL_LBAR_FLSH3 (DIVIL_MSR_BASE + 0x13)
sys/dev/pci/glxreg.h
210
#define DIVIL_LEG_IO (DIVIL_MSR_BASE + 0x14)
sys/dev/pci/glxreg.h
211
#define DIVIL_BALL_OPTS (DIVIL_MSR_BASE + 0x15)
sys/dev/pci/glxreg.h
212
#define DIVIL_SOFT_IRQ (DIVIL_MSR_BASE + 0x16)
sys/dev/pci/glxreg.h
213
#define DIVIL_SOFT_RESET (DIVIL_MSR_BASE + 0x17)
sys/dev/pci/glxreg.h
214
#define NORF_CTL (DIVIL_MSR_BASE + 0x18)
sys/dev/pci/glxreg.h
215
#define NORF_T01 (DIVIL_MSR_BASE + 0x19)
sys/dev/pci/glxreg.h
216
#define NORF_T23 (DIVIL_MSR_BASE + 0x1a)
sys/dev/pci/glxreg.h
217
#define NANDF_DATA (DIVIL_MSR_BASE + 0x1b)
sys/dev/pci/glxreg.h
218
#define NANDF_CTL (DIVIL_MSR_BASE + 0x1c)
sys/dev/pci/glxreg.h
219
#define NANDF_RSVD (DIVIL_MSR_BASE + 0x1d)
sys/dev/pci/glxreg.h
220
#define DIVIL_AC_DMA (DIVIL_MSR_BASE + 0x1e)
sys/dev/pci/glxreg.h
221
#define KELX_CTL (DIVIL_MSR_BASE + 0x1f)
sys/dev/pci/glxreg.h
222
#define PIC_YSEL_LOW (DIVIL_MSR_BASE + 0x20)
sys/dev/pci/glxreg.h
223
#define PIC_YSEL_HIGH (DIVIL_MSR_BASE + 0x21)
sys/dev/pci/glxreg.h
224
#define PIC_ZSEL_LOW (DIVIL_MSR_BASE + 0x22)
sys/dev/pci/glxreg.h
225
#define PIC_ZSEL_HIGH (DIVIL_MSR_BASE + 0x23)
sys/dev/pci/glxreg.h
226
#define PIC_IRQM_PRIM (DIVIL_MSR_BASE + 0x24)
sys/dev/pci/glxreg.h
227
#define PIC_IRQM_LPC (DIVIL_MSR_BASE + 0x25)
sys/dev/pci/glxreg.h
228
#define PIC_XIRR_STS_LOW (DIVIL_MSR_BASE + 0x26)
sys/dev/pci/glxreg.h
229
#define PIC_XIRR_STS_HIGH (DIVIL_MSR_BASE + 0x27)
sys/dev/pci/glxreg.h
230
#define MFGPT_IRQ (DIVIL_MSR_BASE + 0x28)
sys/dev/pci/glxreg.h
231
#define MFGPT_NR (DIVIL_MSR_BASE + 0x29)
sys/dev/pci/glxreg.h
232
#define MFGPT_RSVD (DIVIL_MSR_BASE + 0x2a)
sys/dev/pci/glxreg.h
233
#define MFGPT_SETUP (DIVIL_MSR_BASE + 0x2b)
sys/dev/pci/glxreg.h
234
#define FLPY_3F2_SHDW (DIVIL_MSR_BASE + 0x30)
sys/dev/pci/glxreg.h
235
#define FLPY_3F7_SHDW (DIVIL_MSR_BASE + 0x31)
sys/dev/pci/glxreg.h
236
#define FLPY_372_SHDW (DIVIL_MSR_BASE + 0x32)
sys/dev/pci/glxreg.h
237
#define FLPY_377_SHDW (DIVIL_MSR_BASE + 0x33)
sys/dev/pci/glxreg.h
238
#define PIC_SHDW (DIVIL_MSR_BASE + 0x34)
sys/dev/pci/glxreg.h
239
#define PIT_SHDW (DIVIL_MSR_BASE + 0x36)
sys/dev/pci/glxreg.h
240
#define PIT_CNTRL (DIVIL_MSR_BASE + 0x37)
sys/dev/pci/glxreg.h
241
#define UART1_MOD (DIVIL_MSR_BASE + 0x38)
sys/dev/pci/glxreg.h
242
#define UART1_DONG (DIVIL_MSR_BASE + 0x39)
sys/dev/pci/glxreg.h
243
#define UART1_CONF (DIVIL_MSR_BASE + 0x3a)
sys/dev/pci/glxreg.h
244
#define UART1_RSVD_MSR (DIVIL_MSR_BASE + 0x3b)
sys/dev/pci/glxreg.h
245
#define UART2_MOD (DIVIL_MSR_BASE + 0x3c)
sys/dev/pci/glxreg.h
246
#define UART2_DONG (DIVIL_MSR_BASE + 0x3d)
sys/dev/pci/glxreg.h
247
#define UART2_CONF (DIVIL_MSR_BASE + 0x3e)
sys/dev/pci/glxreg.h
248
#define UART2_RSVD_MSR (DIVIL_MSR_BASE + 0x3f)
sys/dev/pci/glxreg.h
249
#define DMA_MAP (DIVIL_MSR_BASE + 0x40)
sys/dev/pci/glxreg.h
250
#define DMA_SHDW_CH0 (DIVIL_MSR_BASE + 0x41)
sys/dev/pci/glxreg.h
251
#define DMA_SHDW_CH1 (DIVIL_MSR_BASE + 0x42)
sys/dev/pci/glxreg.h
252
#define DMA_SHDW_CH2 (DIVIL_MSR_BASE + 0x43)
sys/dev/pci/glxreg.h
253
#define DMA_SHDW_CH3 (DIVIL_MSR_BASE + 0x44)
sys/dev/pci/glxreg.h
254
#define DMA_SHDW_CH4 (DIVIL_MSR_BASE + 0x45)
sys/dev/pci/glxreg.h
255
#define DMA_SHDW_CH5 (DIVIL_MSR_BASE + 0x46)
sys/dev/pci/glxreg.h
256
#define DMA_SHDW_CH6 (DIVIL_MSR_BASE + 0x47)
sys/dev/pci/glxreg.h
257
#define DMA_SHDW_CH7 (DIVIL_MSR_BASE + 0x48)
sys/dev/pci/glxreg.h
258
#define DMA_MSK_SHDW (DIVIL_MSR_BASE + 0x49)
sys/dev/pci/glxreg.h
259
#define LPC_EADDR (DIVIL_MSR_BASE + 0x4c)
sys/dev/pci/glxreg.h
260
#define LPC_ESTAT (DIVIL_MSR_BASE + 0x4d)
sys/dev/pci/glxreg.h
261
#define LPC_SIRQ (DIVIL_MSR_BASE + 0x4e)
sys/dev/pci/glxreg.h
262
#define LPC_RSVD (DIVIL_MSR_BASE + 0x4f)
sys/dev/pci/glxreg.h
263
#define PMC_LTMR (DIVIL_MSR_BASE + 0x50)
sys/dev/pci/glxreg.h
264
#define PMC_RSVD (DIVIL_MSR_BASE + 0x51)
sys/dev/pci/glxreg.h
265
#define RTC_RAM_LOCK (DIVIL_MSR_BASE + 0x54)
sys/dev/pci/glxreg.h
266
#define RTC_DOMA_OFFSET (DIVIL_MSR_BASE + 0x55)
sys/dev/pci/glxreg.h
267
#define RTC_MONA_OFFSET (DIVIL_MSR_BASE + 0x56)
sys/dev/pci/glxreg.h
268
#define RTC_CEN_OFFSET (DIVIL_MSR_BASE + 0x57)