sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9126

offdelay = DIV64_U64_ROUND_UP((u64)5 * 3 * 10 *

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9138

offdelay = DIV64_U64_ROUND_UP((u64)20 *

sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

906

return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));

sys/dev/pci/drm/display/drm_dp_mst_topology.c

4819

return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4),

sys/dev/pci/drm/i915/display/intel_audio.c

485

hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

118

int_sqrt(DIV64_U64_ROUND_UP(interpolated_product, vco_div_refclk_float) *

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

123

adjusted_vco_clk2 = 1460281 * DIV64_U64_ROUND_UP(scaled_interpolated_sqrt *

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

127

*ana_cp_prop = DIV64_U64_ROUND_UP(adjusted_vco_clk2, curve_2_scaled2);

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

44

dydx = DIV64_U64_ROUND_UP((y2 - y1) * 100000, (x2 - x1));

sys/dev/pci/drm/i915/display/intel_snps_hdmi_pll.c

46

return (y1 + DIV64_U64_ROUND_UP(dydx * (x - x1), 100000));

sys/dev/pci/drm/i915/display/skl_watermark.c

1393

DIV64_U64_ROUND_UP(iter->size * data_rate,