sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5548

bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c

5555

if (writeback) {

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2889

bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;

sys/dev/pci/drm/amd/amdgpu/gfx_v9_4_3.c

2893

amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6690

CalculateWatermarks_params->WritebackEnable = mode_lib->ms.cache_display_cfg.writeback.WritebackEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6691

CalculateWatermarks_params->WritebackPixelFormat = mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6692

CalculateWatermarks_params->WritebackDestinationWidth = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6693

CalculateWatermarks_params->WritebackDestinationHeight = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6694

CalculateWatermarks_params->WritebackSourceHeight = mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6827

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6828

&& mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k] == dml_444_64) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6829

mode_lib->ms.WriteBandwidth[k] = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6830

* mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6831

/ (mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6834

} else if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6835

mode_lib->ms.WriteBandwidth[k] = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6836

* mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6837

/ (mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6848

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true &&

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6857

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6870

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6871

if (mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k] > mode_lib->ms.ip.writeback_max_hscl_ratio

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6872

|| mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k] > mode_lib->ms.ip.writeback_max_vscl_ratio

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6873

|| mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k] < mode_lib->ms.ip.writeback_min_hscl_ratio

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6874

|| mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k] < mode_lib->ms.ip.writeback_min_vscl_ratio

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6875

|| mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k] > (dml_uint_t) mode_lib->ms.ip.writeback_max_hscl_taps

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6876

|| mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k] > (dml_uint_t) mode_lib->ms.ip.writeback_max_vscl_taps

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6877

|| mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k] > (dml_uint_t) mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6878

|| mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k] > (dml_uint_t) mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k]

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6879

|| (mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k] > 2.0 && ((mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k] % 2) == 1))) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

6882

if (2.0 * mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k] * (mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k] - 1) * 57 > mode_lib->ms.ip.writeback_line_buffer_buffer_size) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7204

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k]) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7206

CalculateWriteBackDISPCLK(mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7208

mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7209

mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7210

mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7211

mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7212

mode_lib->ms.cache_display_cfg.writeback.WritebackSourceWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7213

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7847

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7849

mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7850

mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7851

mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7852

mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7853

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7854

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7855

mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7861

if (mode_lib->ms.cache_display_cfg.plane.BlendingAndTiming[m] == k && mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[m] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7864

mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[m],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7865

mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[m],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7866

mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[m],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7867

mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[m],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7868

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[m],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7869

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[m],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

7870

mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[m],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8341

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k]) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8346

mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8348

mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8349

mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8350

mode_lib->ms.cache_display_cfg.writeback.WritebackHTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8351

mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8352

mode_lib->ms.cache_display_cfg.writeback.WritebackSourceWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8353

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8827

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8831

mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8832

mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8833

mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8834

mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8835

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8836

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8837

mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8843

&& mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[j] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8849

mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[j],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8850

mode_lib->ms.cache_display_cfg.writeback.WritebackHRatio[j],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8851

mode_lib->ms.cache_display_cfg.writeback.WritebackVRatio[j],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8852

mode_lib->ms.cache_display_cfg.writeback.WritebackVTaps[j],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8853

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[j],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8854

mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[j],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

8855

mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[j],

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9455

CalculateWatermarks_params->WritebackEnable = mode_lib->ms.cache_display_cfg.writeback.WritebackEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9456

CalculateWatermarks_params->WritebackPixelFormat = mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9457

CalculateWatermarks_params->WritebackDestinationWidth = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9458

CalculateWatermarks_params->WritebackDestinationHeight = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9459

CalculateWatermarks_params->WritebackSourceHeight = mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9484

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9739

if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true && mode_lib->ms.cache_display_cfg.writeback.WritebackPixelFormat[k] == dml_444_32) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9740

s->WRBandwidth = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k] /

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9741

(mode_lib->ms.cache_display_cfg.timing.HTotal[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 4;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9742

} else if (mode_lib->ms.cache_display_cfg.writeback.WritebackEnable[k] == true) {

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9743

s->WRBandwidth = mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationWidth[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackDestinationHeight[k] /

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9744

(mode_lib->ms.cache_display_cfg.timing.HTotal[k] * mode_lib->ms.cache_display_cfg.writeback.WritebackSourceHeight[k] / mode_lib->ms.cache_display_cfg.timing.PixelClock[k]) * 8;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9814

CalculateStutterEfficiency_params->WritebackEnable = mode_lib->ms.cache_display_cfg.writeback.WritebackEnable;

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core.c

9886

mode_lib->ms.cache_display_cfg.writeback.WritebackEnable,

sys/dev/pci/drm/amd/display/dc/dml2/display_mode_core_structs.h

682

struct dml_writeback_cfg_st writeback;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/dcn4_soc_bb.h

175

.writeback = {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/dcn4_soc_bb.h

49

.writeback = {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h

409

struct dml2_writeback_cfg writeback;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h

80

} writeback;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10255

if (p->display_cfg->stream_descriptors[k].writeback.active_writebacks_per_stream > 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10953

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10955

mode_lib->soc.qos_parameters.writeback.base_latency_us

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10957

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10958

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10959

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10960

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10961

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10962

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

10963

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11657

s->mmSOCParameters.WritebackLatency = mode_lib->soc.qos_parameters.writeback.base_latency_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11718

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11906

if (display_cfg->stream_descriptors[k].writeback.active_writebacks_per_stream > 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11907

s->WRBandwidth = display_cfg->stream_descriptors[k].writeback.writeback_stream[0].output_height

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11908

* display_cfg->stream_descriptors[k].writeback.writeback_stream[0].output_width /

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11909

(display_cfg->stream_descriptors[k].timing.h_total * display_cfg->stream_descriptors[k].writeback.writeback_stream[0].input_height

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

11911

* (display_cfg->stream_descriptors[k].writeback.writeback_stream[0].pixel_format == dml2_444_32 ? 4.0 : 8.0);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6726

if (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6838

if (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6840

/ ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6841

* (double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6842

/ ((double)p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height * (double)h_total / pixel_clock_mhz) * 4.0);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

6843

if (p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format == dml2_444_64) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

7862

s->mSOCParameters.WritebackLatency = mode_lib->soc.qos_parameters.writeback.base_latency_us;

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8094

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0 && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format == dml2_444_64) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8095

mode_lib->ms.WriteBandwidth[k][0] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8096

* display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8097

/ (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8100

} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8101

mode_lib->ms.WriteBandwidth[k][0] = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8102

* display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8103

/ (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8114

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0 &&

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8115

(mode_lib->ms.WriteBandwidth[k][0] > mode_lib->ip.writeback_interface_buffer_size_kbytes * 1024 / ((double)mode_lib->soc.qos_parameters.writeback.base_latency_us))) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8124

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8125

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio > mode_lib->ip.writeback_max_hscl_ratio

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8126

|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio > mode_lib->ip.writeback_max_vscl_ratio

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8127

|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio < mode_lib->ip.writeback_min_hscl_ratio

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8128

|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio < mode_lib->ip.writeback_min_vscl_ratio

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8129

|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps > (unsigned int) mode_lib->ip.writeback_max_hscl_taps

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8130

|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps > (unsigned int) mode_lib->ip.writeback_max_vscl_taps

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8131

|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio > (unsigned int)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8132

|| display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio > (unsigned int)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8133

|| (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps > 2.0 && ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps % 2) == 1))) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8136

if (2.0 * display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height * (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps - 1) * 57 > mode_lib->ip.writeback_line_buffer_buffer_size) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8564

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8566

CalculateWriteBackDISPCLK(display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8568

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8569

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8570

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_taps,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8571

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8572

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_width,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8573

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

8605

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9157

if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.active_writebacks_per_stream > 0) {

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9158

mode_lib->ms.WritebackDelayTime[k] = mode_lib->soc.qos_parameters.writeback.base_latency_us + CalculateWriteBackDelay(

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9159

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].pixel_format,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9160

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].h_ratio,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9161

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_ratio,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9162

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].v_taps,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9163

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_width,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9164

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].output_height,

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

9165

display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.writeback_stream[0].input_height,

sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c

1336

populate_dml_writeback_cfg_from_stream_state(&dml_dispcfg->writeback,

sys/dev/pci/drm/include/drm/ttm/ttm_backup.h

63

bool writeback, pgoff_t idx, gfp_t page_gfp,

sys/dev/pci/drm/include/drm/ttm/ttm_bo.h

246

u32 writeback : 1;

sys/dev/pci/drm/include/drm/ttm/ttm_tt.h

298

u32 writeback : 1;

sys/dev/pci/drm/ttm/ttm_backup.c

106

bool writeback, pgoff_t idx, gfp_t page_gfp,

sys/dev/pci/drm/ttm/ttm_backup.c

127

if (writeback && !folio_mapped(to_folio) &&

sys/dev/pci/drm/ttm/ttm_bo_util.c

1130

.writeback = flags.writeback});

sys/dev/pci/drm/ttm/ttm_pool.c

1204

shandle = ttm_backup_backup_page(backup, page, flags->writeback, i,

sys/net/pf_norm.c

1254

struct pf_state_peer *dst, int *writeback)

sys/net/pf_norm.c

1355

*writeback = 1;

usr.bin/mail/extern.h

256

int writeback(FILE *);

usr.bin/mail/quit.c

174

writeback(rbuf);

usr.bin/mail/quit.c

290

writeback(rbuf);