writel
ops->writel(handle, offset, val);
ops->writel(handle, offset, val);
void (*writel)(void *, u_int32_t, u_int32_t);
writel(reg_addr, pcie_index_offset);
writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
writel(0, pcie_index_hi_offset);
writel(reg_addr, pcie_index_offset);
writel(reg_addr + 4, pcie_index_offset);
writel(reg_addr, pcie_index_offset);
writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
writel(reg_addr + 4, pcie_index_offset);
writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
writel(0, pcie_index_hi_offset);
writel(reg_addr, pcie_index_offset);
writel(reg_data, pcie_data_offset);
writel(reg_addr, pcie_index_offset);
writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
writel(reg_data, pcie_data_offset);
writel(0, pcie_index_hi_offset);
writel(reg_addr, pcie_index_offset);
writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
writel(reg_addr + 4, pcie_index_offset);
writel((u32)(reg_data >> 32), pcie_data_offset);
writel(reg_addr, pcie_index_offset);
writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset);
writel(reg_addr + 4, pcie_index_offset);
writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset);
writel((u32)(reg_data >> 32), pcie_data_offset);
writel(0, pcie_index_hi_offset);
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
writel(reg_addr, pcie_index_offset);
writel(v, adev->doorbell.cpu_addr + index);
writel(v, scratch_reg2);
writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
writel(v, scratch_reg3);
writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
writel(v, scratch_reg0);
writel((offset | flag), scratch_reg1);
writel(1, spare_int);
writel(value, db);
writel(lower_32_bits(desc), execlists->submit_reg + port * 2);
writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1);
writel(upper_32_bits(desc), execlists->submit_reg);
writel(lower_32_bits(desc), execlists->submit_reg);
writel(EL_CTRL_LOAD, execlists->ctrl_reg);
#define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
#define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
writel(value, base + i915_mmio_reg_offset(reg))
#define writel_relaxed(v, p) writel(v, p)
writel(v, rdev->doorbell.ptr + index);
writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
writel(entry, ((void __iomem *)ptr) + (i * 4));
writel(v, ((void __iomem *)rdev->rmmio) + reg);
writel((__force u32)cpu_to_le32(0x00000de4), &msg[0]);
writel(0x0, (void __iomem *)&msg[1]);
writel((__force u32)cpu_to_le32(handle), &msg[2]);
writel(0x0, &msg[3]);
writel(0x0, &msg[4]);
writel(0x0, &msg[5]);
writel(0x0, &msg[6]);
writel((__force u32)cpu_to_le32(0x00000780), &msg[7]);
writel((__force u32)cpu_to_le32(0x00000440), &msg[8]);
writel(0x0, &msg[9]);
writel((__force u32)cpu_to_le32(0x01b37000), &msg[10]);
writel(0x0, &msg[i]);
writel((__force u32)cpu_to_le32(0x00000de4), &msg[0]);
writel((__force u32)cpu_to_le32(0x00000002), &msg[1]);
writel((__force u32)cpu_to_le32(handle), &msg[2]);
writel(0x0, &msg[3]);
writel(0x0, &msg[i]);