sys/dev/pci/drm/i915/gvt/cmd_parser.c
1029
vgpu_vreg(vgpu, offset) = data;
sys/dev/pci/drm/i915/gvt/cmd_parser.c
957
vreg = &vgpu_vreg(s->vgpu, offset);
sys/dev/pci/drm/i915/gvt/debugfs.c
66
vreg = vgpu_vreg(param->vgpu, offset);
sys/dev/pci/drm/i915/gvt/display.c
53
u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
sys/dev/pci/drm/i915/gvt/display.c
79
if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
sys/dev/pci/drm/i915/gvt/edid.c
147
memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
sys/dev/pci/drm/i915/gvt/edid.c
149
pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK;
sys/dev/pci/drm/i915/gvt/edid.c
188
if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) {
sys/dev/pci/drm/i915/gvt/edid.c
190
vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT;
sys/dev/pci/drm/i915/gvt/edid.c
243
if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset))
sys/dev/pci/drm/i915/gvt/edid.c
277
vgpu_vreg(vgpu, offset) = wvalue;
sys/dev/pci/drm/i915/gvt/edid.c
305
memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
sys/dev/pci/drm/i915/gvt/edid.c
316
memcpy(&vgpu_vreg(vgpu, offset), ®_data, byte_count);
sys/dev/pci/drm/i915/gvt/edid.c
317
memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
sys/dev/pci/drm/i915/gvt/edid.c
338
memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
sys/dev/pci/drm/i915/gvt/edid.c
347
u32 value = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/edid.c
349
if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE))
sys/dev/pci/drm/i915/gvt/edid.c
350
vgpu_vreg(vgpu, offset) |= GMBUS_INUSE;
sys/dev/pci/drm/i915/gvt/edid.c
361
vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE;
sys/dev/pci/drm/i915/gvt/edid.c
392
memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
sys/dev/pci/drm/i915/gvt/edid.c
426
memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
sys/dev/pci/drm/i915/gvt/edid.c
493
vgpu_vreg(vgpu, offset) = value;
sys/dev/pci/drm/i915/gvt/edid.c
500
msg = vgpu_vreg(vgpu, offset + 4);
sys/dev/pci/drm/i915/gvt/edid.c
511
vgpu_vreg(vgpu, offset) =
sys/dev/pci/drm/i915/gvt/edid.c
560
vgpu_vreg(vgpu, offset + 4) = aux_data_for_write;
sys/dev/pci/drm/i915/gvt/execlist.c
117
vgpu_vreg(vgpu, status_reg) = status.ldw;
sys/dev/pci/drm/i915/gvt/execlist.c
118
vgpu_vreg(vgpu, status_reg + 4) = status.udw;
sys/dev/pci/drm/i915/gvt/execlist.c
139
ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg);
sys/dev/pci/drm/i915/gvt/execlist.c
152
vgpu_vreg(vgpu, offset) = status->ldw;
sys/dev/pci/drm/i915/gvt/execlist.c
153
vgpu_vreg(vgpu, offset + 4) = status->udw;
sys/dev/pci/drm/i915/gvt/execlist.c
156
vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;
sys/dev/pci/drm/i915/gvt/execlist.c
262
status.ldw = vgpu_vreg(vgpu, status_reg);
sys/dev/pci/drm/i915/gvt/execlist.c
263
status.udw = vgpu_vreg(vgpu, status_reg + 4);
sys/dev/pci/drm/i915/gvt/execlist.c
516
ctx_status_ptr.dw = vgpu_vreg(vgpu, ctx_status_ptr_reg);
sys/dev/pci/drm/i915/gvt/execlist.c
519
vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;
sys/dev/pci/drm/i915/gvt/execlist.c
98
status.ldw = vgpu_vreg(vgpu, status_reg);
sys/dev/pci/drm/i915/gvt/execlist.c
99
status.udw = vgpu_vreg(vgpu, status_reg + 4);
sys/dev/pci/drm/i915/gvt/handlers.c
1002
vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
sys/dev/pci/drm/i915/gvt/handlers.c
1012
data = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
1015
vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
sys/dev/pci/drm/i915/gvt/handlers.c
1017
vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
sys/dev/pci/drm/i915/gvt/handlers.c
103
memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
sys/dev/pci/drm/i915/gvt/handlers.c
1033
vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
1055
vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
1077
vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
1080
vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
1083
if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC)
sys/dev/pci/drm/i915/gvt/handlers.c
109
memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
sys/dev/pci/drm/i915/gvt/handlers.c
1133
vgpu_vreg(vgpu, reg) = value;
sys/dev/pci/drm/i915/gvt/handlers.c
1197
data = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
1213
vgpu_vreg(vgpu, offset) = 0;
sys/dev/pci/drm/i915/gvt/handlers.c
1221
msg = vgpu_vreg(vgpu, offset + 4);
sys/dev/pci/drm/i915/gvt/handlers.c
1241
vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
sys/dev/pci/drm/i915/gvt/handlers.c
1258
u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
sys/dev/pci/drm/i915/gvt/handlers.c
1280
vgpu_vreg(vgpu, offset + 4) = 0;
sys/dev/pci/drm/i915/gvt/handlers.c
1299
vgpu_vreg(vgpu, offset + 4) = 0;
sys/dev/pci/drm/i915/gvt/handlers.c
1300
vgpu_vreg(vgpu, offset + 8) = 0;
sys/dev/pci/drm/i915/gvt/handlers.c
1301
vgpu_vreg(vgpu, offset + 12) = 0;
sys/dev/pci/drm/i915/gvt/handlers.c
1302
vgpu_vreg(vgpu, offset + 16) = 0;
sys/dev/pci/drm/i915/gvt/handlers.c
1303
vgpu_vreg(vgpu, offset + 20) = 0;
sys/dev/pci/drm/i915/gvt/handlers.c
1312
vgpu_vreg(vgpu, offset + 4 * idx) = 0;
sys/dev/pci/drm/i915/gvt/handlers.c
1334
vgpu_vreg(vgpu, offset +
sys/dev/pci/drm/i915/gvt/handlers.c
1367
vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
sys/dev/pci/drm/i915/gvt/handlers.c
1423
vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, sbi_offset);
sys/dev/pci/drm/i915/gvt/handlers.c
1435
data = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
1443
vgpu_vreg(vgpu, offset) = data;
sys/dev/pci/drm/i915/gvt/handlers.c
1601
if (vgpu_vreg(vgpu, offset) &
sys/dev/pci/drm/i915/gvt/handlers.c
1603
vgpu_vreg(vgpu, offset) |=
sys/dev/pci/drm/i915/gvt/handlers.c
1606
vgpu_vreg(vgpu, offset) &=
sys/dev/pci/drm/i915/gvt/handlers.c
1616
if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST)
sys/dev/pci/drm/i915/gvt/handlers.c
1617
vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE;
sys/dev/pci/drm/i915/gvt/handlers.c
1619
vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE;
sys/dev/pci/drm/i915/gvt/handlers.c
1629
if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
sys/dev/pci/drm/i915/gvt/handlers.c
1630
vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
sys/dev/pci/drm/i915/gvt/handlers.c
1641
mode = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
1682
if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
sys/dev/pci/drm/i915/gvt/handlers.c
1685
if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
sys/dev/pci/drm/i915/gvt/handlers.c
1688
if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
sys/dev/pci/drm/i915/gvt/handlers.c
1691
if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
sys/dev/pci/drm/i915/gvt/handlers.c
1694
vgpu_vreg(vgpu, offset) = v;
sys/dev/pci/drm/i915/gvt/handlers.c
1812
vgpu_vreg(vgpu, offset) = v;
sys/dev/pci/drm/i915/gvt/handlers.c
1825
vgpu_vreg(vgpu, offset) = v;
sys/dev/pci/drm/i915/gvt/handlers.c
1838
vgpu_vreg(vgpu, offset) = v;
sys/dev/pci/drm/i915/gvt/handlers.c
1851
vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;
sys/dev/pci/drm/i915/gvt/handlers.c
1854
vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;
sys/dev/pci/drm/i915/gvt/handlers.c
1855
vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;
sys/dev/pci/drm/i915/gvt/handlers.c
1859
vgpu_vreg(vgpu, offset) = v;
sys/dev/pci/drm/i915/gvt/handlers.c
1867
u32 v = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
1871
vgpu_vreg(vgpu, offset) = v;
sys/dev/pci/drm/i915/gvt/handlers.c
1882
vgpu_vreg(vgpu, offset - 0x600) = v;
sys/dev/pci/drm/i915/gvt/handlers.c
1883
vgpu_vreg(vgpu, offset - 0x800) = v;
sys/dev/pci/drm/i915/gvt/handlers.c
1885
vgpu_vreg(vgpu, offset - 0x400) = v;
sys/dev/pci/drm/i915/gvt/handlers.c
1886
vgpu_vreg(vgpu, offset - 0x600) = v;
sys/dev/pci/drm/i915/gvt/handlers.c
1889
vgpu_vreg(vgpu, offset) = v;
sys/dev/pci/drm/i915/gvt/handlers.c
1914
vgpu_vreg(vgpu, offset) = v;
sys/dev/pci/drm/i915/gvt/handlers.c
1922
vgpu_vreg(vgpu, offset) = 0;
sys/dev/pci/drm/i915/gvt/handlers.c
1949
vgpu_vreg(vgpu, offset) = lower_32_bits(pat);
sys/dev/pci/drm/i915/gvt/handlers.c
1960
vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET;
sys/dev/pci/drm/i915/gvt/handlers.c
1985
vgpu_vreg(vgpu, offset) =
sys/dev/pci/drm/i915/gvt/handlers.c
2100
vgpu_vreg(vgpu, offset) = 0;
sys/dev/pci/drm/i915/gvt/handlers.c
2132
data = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
2139
vgpu_vreg(vgpu, offset) = data;
sys/dev/pci/drm/i915/gvt/handlers.c
297
old = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
3118
old_vreg = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
3120
mask = vgpu_vreg(vgpu, offset) >> 16;
sys/dev/pci/drm/i915/gvt/handlers.c
3121
vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |
sys/dev/pci/drm/i915/gvt/handlers.c
3122
(vgpu_vreg(vgpu, offset) & mask);
sys/dev/pci/drm/i915/gvt/handlers.c
3179
old_vreg = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
3191
data |= vgpu_vreg(vgpu, offset) & ro_mask;
sys/dev/pci/drm/i915/gvt/handlers.c
3197
u32 mask = vgpu_vreg(vgpu, offset) >> 16;
sys/dev/pci/drm/i915/gvt/handlers.c
3199
vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
sys/dev/pci/drm/i915/gvt/handlers.c
320
vgpu_vreg(vgpu, offset) = new;
sys/dev/pci/drm/i915/gvt/handlers.c
3200
| (vgpu_vreg(vgpu, offset) & mask);
sys/dev/pci/drm/i915/gvt/handlers.c
321
vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
sys/dev/pci/drm/i915/gvt/handlers.c
3233
intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset));
sys/dev/pci/drm/i915/gvt/handlers.c
332
data = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
369
vgpu_vreg(vgpu, offset) = 0;
sys/dev/pci/drm/i915/gvt/handlers.c
391
if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
sys/dev/pci/drm/i915/gvt/handlers.c
409
if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
sys/dev/pci/drm/i915/gvt/handlers.c
410
vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
sys/dev/pci/drm/i915/gvt/handlers.c
412
vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
sys/dev/pci/drm/i915/gvt/handlers.c
421
if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
sys/dev/pci/drm/i915/gvt/handlers.c
422
vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
sys/dev/pci/drm/i915/gvt/handlers.c
424
vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
sys/dev/pci/drm/i915/gvt/handlers.c
426
if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
sys/dev/pci/drm/i915/gvt/handlers.c
427
vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
sys/dev/pci/drm/i915/gvt/handlers.c
429
vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
sys/dev/pci/drm/i915/gvt/handlers.c
442
vgpu_vreg(vgpu, offset) = 1 << 17;
sys/dev/pci/drm/i915/gvt/handlers.c
445
vgpu_vreg(vgpu, offset) = 0x3;
sys/dev/pci/drm/i915/gvt/handlers.c
448
vgpu_vreg(vgpu, offset) = 0x2f << 16;
sys/dev/pci/drm/i915/gvt/handlers.c
718
data = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/handlers.c
721
vgpu_vreg(vgpu, offset) |= TRANSCONF_STATE_ENABLE;
sys/dev/pci/drm/i915/gvt/handlers.c
725
vgpu_vreg(vgpu, offset) &= ~TRANSCONF_STATE_ENABLE;
sys/dev/pci/drm/i915/gvt/handlers.c
813
if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
sys/dev/pci/drm/i915/gvt/handlers.c
814
vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
sys/dev/pci/drm/i915/gvt/handlers.c
816
vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
sys/dev/pci/drm/i915/gvt/handlers.c
827
vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
sys/dev/pci/drm/i915/gvt/handlers.c
837
u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
sys/dev/pci/drm/i915/gvt/handlers.c
970
data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
sys/dev/pci/drm/i915/gvt/handlers.c
987
vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
sys/dev/pci/drm/i915/gvt/handlers.c
988
(vgpu_vreg(vgpu, offset) & sticky_mask);
sys/dev/pci/drm/i915/gvt/handlers.c
989
vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
sys/dev/pci/drm/i915/gvt/handlers.c
999
data = vgpu_vreg(vgpu, offset);
sys/dev/pci/drm/i915/gvt/interrupt.c
202
trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),
sys/dev/pci/drm/i915/gvt/interrupt.c
203
(vgpu_vreg(vgpu, reg) ^ imr));
sys/dev/pci/drm/i915/gvt/interrupt.c
205
vgpu_vreg(vgpu, reg) = imr;
sys/dev/pci/drm/i915/gvt/interrupt.c
231
u32 virtual_ier = vgpu_vreg(vgpu, reg);
sys/dev/pci/drm/i915/gvt/interrupt.c
243
vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL;
sys/dev/pci/drm/i915/gvt/interrupt.c
244
vgpu_vreg(vgpu, reg) |= ier;
sys/dev/pci/drm/i915/gvt/interrupt.c
273
trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg),
sys/dev/pci/drm/i915/gvt/interrupt.c
274
(vgpu_vreg(vgpu, reg) ^ ier));
sys/dev/pci/drm/i915/gvt/interrupt.c
276
vgpu_vreg(vgpu, reg) = ier;
sys/dev/pci/drm/i915/gvt/interrupt.c
311
trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
sys/dev/pci/drm/i915/gvt/interrupt.c
312
(vgpu_vreg(vgpu, reg) ^ iir));
sys/dev/pci/drm/i915/gvt/interrupt.c
317
vgpu_vreg(vgpu, reg) &= ~iir;
sys/dev/pci/drm/i915/gvt/interrupt.c
351
u32 val = vgpu_vreg(vgpu,
sys/dev/pci/drm/i915/gvt/interrupt.c
353
& vgpu_vreg(vgpu,
sys/dev/pci/drm/i915/gvt/interrupt.c
383
vgpu_vreg(vgpu, isr) &= ~clear_bits;
sys/dev/pci/drm/i915/gvt/interrupt.c
384
vgpu_vreg(vgpu, isr) |= set_bits;
sys/dev/pci/drm/i915/gvt/interrupt.c
391
vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));
sys/dev/pci/drm/i915/gvt/interrupt.c
473
if (!test_bit(bit, (void *)&vgpu_vreg(vgpu,
sys/dev/pci/drm/i915/gvt/interrupt.c
476
set_bit(bit, (void *)&vgpu_vreg(vgpu,
sys/dev/pci/drm/i915/gvt/interrupt.c
528
if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
sys/dev/pci/drm/i915/gvt/interrupt.c
540
if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base))
sys/dev/pci/drm/i915/gvt/interrupt.c
541
& vgpu_vreg(vgpu, regbase_to_ier(reg_base))))
sys/dev/pci/drm/i915/gvt/interrupt.c
545
if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))
sys/dev/pci/drm/i915/gvt/scheduler.c
274
vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
sys/dev/pci/drm/i915/gvt/scheduler.c
278
vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
sys/dev/pci/drm/i915/gvt/scheduler.c
282
vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
