sys/dev/pci/drm/i915/gt/intel_workarounds.c

1174

wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1278

wa_write_clr_set(wal, steering_reg, mcr_mask, mcr);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

1426

wa_write_clr_set(wal,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2352

wa_write_clr_set(wal,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2356

wa_write_clr_set(wal,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2499

wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2530

wa_write_clr_set(wal,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2564

wa_write_clr_set(wal,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

260

wa_write_clr_set(wal, reg, ~0, set);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

266

wa_write_clr_set(wal, reg, set, set);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

278

wa_write_clr_set(wal, reg, clr, 0);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

682

wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

905

wa_write_clr_set(wal,