sys/dev/pci/drm/i915/gt/intel_workarounds.c

2375

wa_mcr_write_clr_set(wal,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2487

wa_mcr_write_clr_set(wal,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2501

wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2503

wa_mcr_write_clr_set(wal, GEN9_SCRATCH1,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

272

wa_mcr_write_clr_set(wal, reg, set, set);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2728

wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

284

wa_mcr_write_clr_set(wal, reg, clr, 0);

sys/dev/pci/drm/i915/gt/intel_workarounds.c

2864

wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

707

wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,

sys/dev/pci/drm/i915/gt/intel_workarounds.c

709

wa_mcr_write_clr_set(wal, XEHP_FF_MODE2, FF_MODE2_TDS_TIMER_MASK,