sys/arch/amd64/amd64/vmm_machdep.c

148

void vmx_setmsrbrw(struct vcpu *, uint32_t);

sys/arch/amd64/amd64/vmm_machdep.c

2500

vmx_setmsrbrw(vcpu, MSR_IA32_FEATURE_CONTROL);

sys/arch/amd64/amd64/vmm_machdep.c

2501

vmx_setmsrbrw(vcpu, MSR_SYSENTER_CS);

sys/arch/amd64/amd64/vmm_machdep.c

2502

vmx_setmsrbrw(vcpu, MSR_SYSENTER_ESP);

sys/arch/amd64/amd64/vmm_machdep.c

2503

vmx_setmsrbrw(vcpu, MSR_SYSENTER_EIP);

sys/arch/amd64/amd64/vmm_machdep.c

2504

vmx_setmsrbrw(vcpu, MSR_EFER);

sys/arch/amd64/amd64/vmm_machdep.c

2505

vmx_setmsrbrw(vcpu, MSR_STAR);

sys/arch/amd64/amd64/vmm_machdep.c

2506

vmx_setmsrbrw(vcpu, MSR_LSTAR);

sys/arch/amd64/amd64/vmm_machdep.c

2507

vmx_setmsrbrw(vcpu, MSR_CSTAR);

sys/arch/amd64/amd64/vmm_machdep.c

2508

vmx_setmsrbrw(vcpu, MSR_SFMASK);

sys/arch/amd64/amd64/vmm_machdep.c

2509

vmx_setmsrbrw(vcpu, MSR_FSBASE);

sys/arch/amd64/amd64/vmm_machdep.c

2510

vmx_setmsrbrw(vcpu, MSR_GSBASE);

sys/arch/amd64/amd64/vmm_machdep.c

2511

vmx_setmsrbrw(vcpu, MSR_KERNELGSBASE);

sys/arch/amd64/amd64/vmm_machdep.c

2518

vmx_setmsrbrw(vcpu, MSR_S_CET);