games/grdc/grdc.c

191

vline(ACS_VLINE, YDEPTH);

games/grdc/grdc.c

194

vline(ACS_VLINE, YDEPTH);

lib/libcurses/curses.h

820

extern NCURSES_EXPORT(int) vline (chtype, int); /* generated */

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

100

.vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

105

.vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

110

.vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

115

.vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

120

.vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

3285

if (disp_int & interrupt_status_offsets[crtc].vline)

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

89

uint32_t vline;

sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c

95

.vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

100

uint32_t vline;

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

106

.vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

111

.vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

116

.vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

121

.vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

126

.vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

131

.vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v6_0.c

3102

if (disp_int & interrupt_status_offsets[crtc].vline)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

104

.vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

109

.vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

114

.vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

119

.vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

3118

if (disp_int & interrupt_status_offsets[crtc].vline)

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

88

uint32_t vline;

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

94

.vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,

sys/dev/pci/drm/amd/amdgpu/dce_v8_0.c

99

.vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,