sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

294

struct fixed31_32 v_init;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

310

v_init =

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

316

inits->v_init.integer = dc_fixpt_floor(v_init);

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

317

inits->v_init.fraction = dc_fixpt_u0d19(v_init) << 5;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

326

struct fixed31_32 v_init;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

339

v_init =

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

345

inits->v_init.integer = dc_fixpt_floor(v_init);

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

346

inits->v_init.fraction = dc_fixpt_u0d19(v_init) << 5;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

366

SCL_V_INIT_INT, inits->v_init.integer,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

367

SCL_V_INIT_FRAC, inits->v_init.fraction);

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

395

SCL_V_INIT_INT, inits->v_init.integer,

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.c

396

SCL_V_INIT_FRAC, inits->v_init.fraction);

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

620

struct init_int_and_frac v_init;

sys/dev/pci/drm/amd/display/dc/dce/dce_transform.h

629

struct init_int_and_frac v_init;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

350

uint32_t v_init;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

360

v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

363

asic_blank_end = v_init -

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

376

v_init = v_init / 2;

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

385

VTG0_VCOUNT_INIT, v_init);

sys/dev/pci/drm/amd/display/dc/optc/dcn10/dcn10_optc.c

387

REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init);

usr.bin/vi/vi/vi.c

39

static int v_init(SCR *);

usr.bin/vi/vi/vi.c

84

if (v_init(sp))