vgpu_cfg_space
memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);
u8 old = vgpu_cfg_space(vgpu)[offset];
u32 *pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY;
memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,
vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] =
vgpu_cfg_space(vgpu)[PCI_CLASS_PROG] =
gmch_ctl = (u16 *)(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_GMCH_CONTROL);
vgpu_cfg_space(vgpu)[PCI_COMMAND] &= ~(PCI_COMMAND_IO
memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4);
memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4);
memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_4, 0, 8);
memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4);
memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4);
if (vgpu_cfg_space(vgpu)[PCI_STATUS] & PCI_STATUS_CAP_LIST) {
next = vgpu_cfg_space(vgpu)[PCI_CAPABILITY_LIST];
if (vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_ID] == PCI_CAP_ID_PM) {
next = vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_NEXT];
u8 cmd = vgpu_cfg_space(vgpu)[PCI_COMMAND];
bool primary = vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] !=
u8 *cfg_base = vgpu_cfg_space(vgpu);
pwr = (pci_power_t __force)(*(u16*)(&vgpu_cfg_space(vgpu)[off])
pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
control = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_CONTROL(offset));
addr = *(u32 *)(vgpu_cfg_space(vgpu) + MSI_CAP_ADDRESS(offset));
data = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_DATA(offset));
if ((vgpu_cfg_space(vgpu)[INTEL_GVT_PCI_SWSCI]