bin/ksh/c_test.c

299

int64_t v1, v2;

bin/ksh/c_test.c

301

if (!evaluate(opnd1, &v1, KSH_RETURN_ERROR, false) ||

bin/ksh/c_test.c

309

return v1 == v2;

bin/ksh/c_test.c

311

return v1 != v2;

bin/ksh/c_test.c

313

return v1 >= v2;

bin/ksh/c_test.c

315

return v1 > v2;

bin/ksh/c_test.c

317

return v1 <= v2;

bin/ksh/c_test.c

319

return v1 < v2;

bin/ps/ps.c

442

pscomp(const void *v1, const void *v2)

bin/ps/ps.c

444

const struct pinfo *p1 = (const struct pinfo *)v1;

games/snake/snake.c

568

double v1, v2, vp, max;

games/snake/snake.c

572

v1 = sqrt((double)(d.col * d.col + d.line * d.line) );

games/snake/snake.c

578

if (v1 > 0)

games/snake/snake.c

579

vp = ((double)vp) / (v1 * v2);

lib/libc/quad/muldi3.c

122

if (u1 == 0 && v1 == 0) {

lib/libc/quad/muldi3.c

142

if (v0 >= v1)

lib/libc/quad/muldi3.c

143

vdiff = v0 - v1;

lib/libc/quad/muldi3.c

145

vdiff = v1 - v0, negmid ^= 1;

lib/libc/quad/muldi3.c

148

high = u1 * v1;

lib/libc/quad/muldi3.c

184

u_int u1, u0, v1, v0, udiff, vdiff, high, mid, low;

lib/libc/quad/muldi3.c

191

v1 = HHALF(v);

lib/libc/quad/muldi3.c

197

if (u1 == 0 && v1 == 0)

lib/libc/quad/muldi3.c

204

if (v0 >= v1)

lib/libc/quad/muldi3.c

205

vdiff = v0 - v1;

lib/libc/quad/muldi3.c

207

vdiff = v1 - v0, neg ^= 1;

lib/libc/quad/muldi3.c

210

high = u1 * v1;

lib/libc/quad/qdivrem.c

176

v1 = v[1]; /* for D3 -- note that v[1..n] are constant */

lib/libc/quad/qdivrem.c

192

if (uj0 == v1) {

lib/libc/quad/qdivrem.c

198

qhat = nn / v1;

lib/libc/quad/qdivrem.c

199

rhat = nn % v1;

lib/libc/quad/qdivrem.c

204

if ((rhat += v1) >= B)

lib/libc/quad/qdivrem.c

69

digit v1, v2;

lib/libcrypto/bf/blowfish.c

515

BF_LONG v0, v1, t;

lib/libcrypto/bf/blowfish.c

527

n2l(iv, v1);

lib/libcrypto/bf/blowfish.c

528

ti[1] = v1;

lib/libcrypto/bf/blowfish.c

547

n2l(iv, v1);

lib/libcrypto/bf/blowfish.c

548

ti[1] = v1;

lib/libcrypto/bf/blowfish.c

564

v0 = v1 = ti[0] = ti[1] = t=c = cc = 0;

lib/libcrypto/bf/blowfish.c

600

BF_LONG v0, v1, t;

lib/libcrypto/bf/blowfish.c

611

n2l(iv, v1);

lib/libcrypto/bf/blowfish.c

613

ti[1] = v1;

lib/libcrypto/bf/blowfish.c

616

l2n(v1, dp);

lib/libcrypto/bf/blowfish.c

632

v1 = ti[1];

lib/libcrypto/bf/blowfish.c

635

l2n(v1, iv);

lib/libcrypto/bf/blowfish.c

637

t = v0 = v1 = ti[0] = ti[1] = 0;

lib/libcrypto/cast/cast.c

857

CAST_LONG v0, v1, t;

lib/libcrypto/cast/cast.c

869

n2l(iv, v1);

lib/libcrypto/cast/cast.c

870

ti[1] = v1;

lib/libcrypto/cast/cast.c

889

n2l(iv, v1);

lib/libcrypto/cast/cast.c

890

ti[1] = v1;

lib/libcrypto/cast/cast.c

906

v0 = v1 = ti[0] = ti[1] = t=c = cc = 0;

lib/libcrypto/cast/cast.c

943

CAST_LONG v0, v1, t;

lib/libcrypto/cast/cast.c

954

n2l(iv, v1);

lib/libcrypto/cast/cast.c

956

ti[1] = v1;

lib/libcrypto/cast/cast.c

959

l2n(v1, dp);

lib/libcrypto/cast/cast.c

975

v1 = ti[1];

lib/libcrypto/cast/cast.c

978

l2n(v1, iv);

lib/libcrypto/cast/cast.c

980

t = v0 = v1 = ti[0] = ti[1] = 0;

lib/libcrypto/des/des.c

148

DES_LONG v0, v1;

lib/libcrypto/des/des.c

159

c2l(iv, v1);

lib/libcrypto/des/des.c

162

ti[1] = v1;

lib/libcrypto/des/des.c

165

v1 = ti[1];

lib/libcrypto/des/des.c

169

l2c(v1, iv);

lib/libcrypto/des/des.c

181

c2l(iv, v1);

lib/libcrypto/des/des.c

184

ti[1] = v1;

lib/libcrypto/des/des.c

187

v1 = ti[1];

lib/libcrypto/des/des.c

191

l2c(v1, iv);

lib/libcrypto/des/des.c

201

v0 = v1 = ti[0] = ti[1] = c = cc = 0;

lib/libcrypto/des/des.c

216

DES_LONG d0, d1, v0, v1;

lib/libcrypto/des/des.c

227

c2l(iv, v1);

lib/libcrypto/des/des.c

232

ti[1] = v1;

lib/libcrypto/des/des.c

243

v0 = v1;

lib/libcrypto/des/des.c

244

v1 = d0;

lib/libcrypto/des/des.c

247

v1 = d1;

lib/libcrypto/des/des.c

251

l2c(v1, iv);

lib/libcrypto/des/des.c

267

c2l(iv, v1);

lib/libcrypto/des/des.c

274

ti[1] = v1;

lib/libcrypto/des/des.c

281

v0 = v1;

lib/libcrypto/des/des.c

282

v1 = d0;

lib/libcrypto/des/des.c

285

v1 = d1;

lib/libcrypto/des/des.c

289

l2c(v1, iv);

lib/libcrypto/des/des.c

305

c2l(iv, v1);

lib/libcrypto/des/des.c

315

l2c(v1, iv);

lib/libcrypto/des/des.c

316

v0 = v1 = d0 = d1 = ti[0] = ti[1] = 0;

lib/libcrypto/des/des.c

330

DES_LONG v0, v1;

lib/libcrypto/des/des.c

342

c2l(iv, v1);

lib/libcrypto/des/des.c

343

ti[1] = v1;

lib/libcrypto/des/des.c

362

c2l(iv, v1);

lib/libcrypto/des/des.c

363

ti[1] = v1;

lib/libcrypto/des/des.c

379

v0 = v1 = ti[0] = ti[1] = c = cc = 0;

lib/libcrypto/des/des.c

397

DES_LONG d0, d1, v0, v1;

lib/libcrypto/des/des.c

413

c2l(iv, v1);

lib/libcrypto/des/des.c

418

ti[1] = v1;

lib/libcrypto/des/des.c

429

v0 = v1;

lib/libcrypto/des/des.c

430

v1 = d0;

lib/libcrypto/des/des.c

433

v1 = d1;

lib/libcrypto/des/des.c

438

l2c(v1, iv);

lib/libcrypto/des/des.c

442

sh[0] = v0, sh[1] = v1, sh[2] = d0, sh[3] = d1;

lib/libcrypto/des/des.c

452

v0 = sh[0], v1 = sh[1];

lib/libcrypto/des/des.c

456

c2l(iv, v1);

lib/libcrypto/des/des.c

464

ti[1] = v1;

lib/libcrypto/des/des.c

471

v0 = v1;

lib/libcrypto/des/des.c

472

v1 = d0;

lib/libcrypto/des/des.c

475

v1 = d1;

lib/libcrypto/des/des.c

480

l2c(v1, iv);

lib/libcrypto/des/des.c

484

sh[0] = v0, sh[1] = v1, sh[2] = d0, sh[3] = d1;

lib/libcrypto/des/des.c

494

v0 = sh[0], v1 = sh[1];

lib/libcrypto/des/des.c

498

c2l(iv, v1);

lib/libcrypto/des/des.c

509

l2c(v1, iv);

lib/libcrypto/des/des.c

510

v0 = v1 = d0 = d1 = ti[0] = ti[1] = 0;

lib/libcrypto/des/des.c

702

DES_LONG v0, v1;

lib/libcrypto/des/des.c

713

c2l(iv, v1);

lib/libcrypto/des/des.c

715

ti[1] = v1;

lib/libcrypto/des/des.c

718

l2c(v1, dp);

lib/libcrypto/des/des.c

725

v1 = ti[1];

lib/libcrypto/des/des.c

729

l2c(v1, dp);

lib/libcrypto/des/des.c

738

l2c(v1, iv);

lib/libcrypto/des/des.c

740

v0 = v1 = ti[0] = ti[1] = 0;

lib/libcrypto/des/des.c

754

DES_LONG v0, v1, t;

lib/libcrypto/des/des.c

765

c2l(iv, v1);

lib/libcrypto/des/des.c

767

ti[1] = v1;

lib/libcrypto/des/des.c

770

l2c(v1, dp);

lib/libcrypto/des/des.c

786

v1 = ti[1];

lib/libcrypto/des/des.c

789

l2c(v1, iv);

lib/libcrypto/des/des.c

791

t = v0 = v1 = ti[0] = ti[1] = 0;

lib/libcrypto/des/des.c

807

DES_LONG d0, d1, vv0, vv1, v0, v1, n = (numbits + 7)/8;

lib/libcrypto/des/des.c

832

c2l(iv, v1);

lib/libcrypto/des/des.c

834

ti[1] = v1;

lib/libcrypto/des/des.c

837

ti[1] = v1;

lib/libcrypto/des/des.c

849

v0 = v1;

lib/libcrypto/des/des.c

850

v1 = vv0;

lib/libcrypto/des/des.c

853

v1 = vv1;

lib/libcrypto/des/des.c

855

v0 = ((v1 >> (num - 32))|(vv0 << (64 - num))) &

lib/libcrypto/des/des.c

857

v1 = ((vv0 >> (num - 32))|(vv1 << (64 - num))) &

lib/libcrypto/des/des.c

860

v0 = ((v0 >> num)|(v1 << (32 - num))) & 0xffffffffL;

lib/libcrypto/des/des.c

861

v1 = ((v1 >> num)|(vv0 << (32 - num))) & 0xffffffffL;

lib/libcrypto/des/des.c

866

l2c(v1, iv);

lib/libcrypto/des/des.c

867

v0 = v1 = d0 = d1 = ti[0] = ti[1] = vv0 = vv1 = 0;

lib/libcrypto/idea/idea.c

188

unsigned long v0, v1, t;

lib/libcrypto/idea/idea.c

200

n2l(iv, v1);

lib/libcrypto/idea/idea.c

201

ti[1] = v1;

lib/libcrypto/idea/idea.c

220

n2l(iv, v1);

lib/libcrypto/idea/idea.c

221

ti[1] = v1;

lib/libcrypto/idea/idea.c

237

v0 = v1 = ti[0] = ti[1] = t = c = cc = 0;

lib/libcrypto/idea/idea.c

271

unsigned long v0, v1, t;

lib/libcrypto/idea/idea.c

282

n2l(iv, v1);

lib/libcrypto/idea/idea.c

284

ti[1] = v1;

lib/libcrypto/idea/idea.c

287

l2n(v1, dp);

lib/libcrypto/idea/idea.c

303

v1 = ti[1];

lib/libcrypto/idea/idea.c

306

l2n(v1, iv);

lib/libcrypto/idea/idea.c

308

t = v0 = v1 = ti[0] = ti[1] = 0;

lib/libcrypto/rc2/rc2.c

329

unsigned long v0, v1, t;

lib/libcrypto/rc2/rc2.c

341

c2l(iv, v1);

lib/libcrypto/rc2/rc2.c

342

ti[1] = v1;

lib/libcrypto/rc2/rc2.c

361

c2l(iv, v1);

lib/libcrypto/rc2/rc2.c

362

ti[1] = v1;

lib/libcrypto/rc2/rc2.c

378

v0 = v1 = ti[0] = ti[1] = t = c = cc = 0;

lib/libcrypto/rc2/rc2.c

421

unsigned long v0, v1, t;

lib/libcrypto/rc2/rc2.c

432

c2l(iv, v1);

lib/libcrypto/rc2/rc2.c

434

ti[1] = v1;

lib/libcrypto/rc2/rc2.c

437

l2c(v1, dp);

lib/libcrypto/rc2/rc2.c

453

v1 = ti[1];

lib/libcrypto/rc2/rc2.c

456

l2c(v1, iv);

lib/libcrypto/rc2/rc2.c

458

t = v0 = v1 = ti[0] = ti[1] = 0;

lib/libexpat/lib/siphash.h

132

uint64_t v0, v1, v2, v3;

lib/libexpat/lib/siphash.h

170

H->v0 += H->v1;

lib/libexpat/lib/siphash.h

171

H->v1 = SIP_ROTL(H->v1, 13);

lib/libexpat/lib/siphash.h

172

H->v1 ^= H->v0;

lib/libexpat/lib/siphash.h

183

H->v2 += H->v1;

lib/libexpat/lib/siphash.h

184

H->v1 = SIP_ROTL(H->v1, 17);

lib/libexpat/lib/siphash.h

185

H->v1 ^= H->v2;

lib/libexpat/lib/siphash.h

193

H->v1 = SIP_ULL(0x646f7261U, 0x6e646f6dU) ^ key->k[1];

lib/libexpat/lib/siphash.h

266

return H->v0 ^ H->v1 ^ H->v2 ^ H->v3;

lib/libm/src/e_lgamma_r.c

125

v1 = 2.45597793713041134822e+00, /* 0x4003A5D7, 0xC2BD619C */

lib/libm/src/e_lgamma_r.c

264

p2 = one+y*(v1+y*(v2+y*(v3+y*(v4+y*v5))));

lib/libm/src/e_lgammaf_r.c

200

p2 = one+y*(v1+y*(v2+y*(v3+y*(v4+y*v5))));

lib/libm/src/e_lgammaf_r.c

61

v1 = 2.4559779167e+00, /* 0x401d2ebe */

lib/libm/src/ld80/e_lgammal.c

157

v1 = 3.399692260848747447377972081399737098610E3L,

lib/libm/src/ld80/e_lgammal.c

378

p2 = v0 + y * (v1 + y * (v2 + y * (v3 + y * (v4 + y * (v5 + y)))));

lib/libpcap/optimize.c

490

int v0, v1;

lib/libpcap/optimize.c

523

F(int code, int v0, int v1)

lib/libpcap/optimize.c

529

hash = (u_int)code ^ (v0 << 4) ^ (v1 << 8);

lib/libpcap/optimize.c

533

if (p->code == code && p->v0 == v0 && p->v1 == v1)

lib/libpcap/optimize.c

546

p->v1 = v1;

lib/libpcap/optimize.c

563

fold_op(struct stmt *s, int v0, int v1)

lib/libpcap/optimize.c

568

b = vmap[v1].const_val;

lib/libssl/d1_pkt.c

132

satsub64be(const unsigned char *v1, const unsigned char *v2)

lib/libssl/d1_pkt.c

145

if (((size_t)v1 | (size_t)v2) & 0x7)

lib/libssl/d1_pkt.c

148

l = *((long *)v1);

lib/libssl/d1_pkt.c

158

ret = (int)v1[7] - (int)v2[7];

lib/libssl/d1_pkt.c

163

brw += (int)v1[i]-(int)v2[i];

lib/libssl/d1_pkt.c

169

brw += (int)v1[i]-(int)v2[i];

regress/lib/libc/locale/check_isw/check_isw.c

31

check_bool(int v1, int v2, char msg)

regress/lib/libc/locale/check_isw/check_isw.c

33

if (!v1 != !v2) {

regress/lib/libc/locale/check_isw/check_isw.c

40

check_value(int v1, int v2, char msg)

regress/lib/libc/locale/check_isw/check_isw.c

42

if (v1 != v2) {

regress/lib/libc/qsort/qsort_test.c

104

cmp_d(const void *v1, const void *v2)

regress/lib/libc/qsort/qsort_test.c

106

const double a = *(const double *)v1;

regress/lib/libc/qsort/qsort_test.c

113

cmp_checked_d(const void *v1, const void *v2)

regress/lib/libc/qsort/qsort_test.c

115

const double a = *(const double *)v1;

regress/lib/libc/qsort/qsort_test.c

46

int (*cmp)(const void *v1, const void *v2);

regress/lib/libc/qsort/qsort_test.c

47

int (*cmp_checked)(const void *v1, const void *v2);

regress/lib/libc/qsort/qsort_test.c

62

cmp_i(const void *v1, const void *v2)

regress/lib/libc/qsort/qsort_test.c

64

const int a = *(const int *)v1;

regress/lib/libc/qsort/qsort_test.c

71

cmp_checked_i(const void *v1, const void *v2)

regress/lib/libc/qsort/qsort_test.c

73

const int a = *(const int *)v1;

regress/lib/libc/qsort/qsort_test.c

83

cmp_ll(const void *v1, const void *v2)

regress/lib/libc/qsort/qsort_test.c

85

const long long a = *(const long long *)v1;

regress/lib/libc/qsort/qsort_test.c

92

cmp_checked_ll(const void *v1, const void *v2)

regress/lib/libc/qsort/qsort_test.c

94

const long long a = *(const long long *)v1;

regress/sys/kern/mmap2/mmaptest.c

28

char *v1, *v2;

regress/sys/kern/mmap2/mmaptest.c

44

v1 = mmap(NULL, 2 * page_size, PROT_READ|PROT_WRITE,

regress/sys/kern/mmap2/mmaptest.c

46

if (v1 == MAP_FAILED)

regress/sys/kern/mmap2/mmaptest.c

51

v2 = mmap(v1 + page_size, page_size, PROT_READ|PROT_WRITE,

regress/sys/kern/mmap2/mmaptest.c

56

memcpy(v1, MAGIC, sizeof(MAGIC));

regress/sys/kern/mmap2/mmaptest.c

61

if (memcmp(v1, v2, sizeof(MAGIC)) != 0)

regress/sys/kern/mmap2/mmaptest.c

64

if (munmap(v1, 2 * page_size) < 0)

sbin/unwind/libunbound/services/view.c

49

view_cmp(const void* v1, const void* v2)

sbin/unwind/libunbound/services/view.c

51

struct view* a = (struct view*)v1;

sbin/unwind/libunbound/services/view.h

115

int view_cmp(const void* v1, const void* v2);

sbin/unwind/libunbound/util/siphash.c

110

v1 ^= k1;

sbin/unwind/libunbound/util/siphash.c

114

v1 ^= 0xee;

sbin/unwind/libunbound/util/siphash.c

182

b = v0 ^ v1 ^ v2 ^ v3;

sbin/unwind/libunbound/util/siphash.c

188

v1 ^= 0xdd;

sbin/unwind/libunbound/util/siphash.c

194

b = v0 ^ v1 ^ v2 ^ v3;

sbin/unwind/libunbound/util/siphash.c

58

v0 += v1; \

sbin/unwind/libunbound/util/siphash.c

59

v1 = ROTL(v1, 13); \

sbin/unwind/libunbound/util/siphash.c

60

v1 ^= v0; \

sbin/unwind/libunbound/util/siphash.c

68

v2 += v1; \

sbin/unwind/libunbound/util/siphash.c

69

v1 = ROTL(v1, 17); \

sbin/unwind/libunbound/util/siphash.c

70

v1 ^= v2; \

sbin/unwind/libunbound/util/siphash.c

79

printf("(%3d) v1 %08x %08x\n", (int)inlen, (uint32_t)(v1 >> 32), \

sbin/unwind/libunbound/util/siphash.c

80

(uint32_t)v1); \

sbin/unwind/libunbound/util/siphash.c

94

uint64_t v1 = 0x646f72616e646f6dULL;

sys/arch/arm/arm/fault.c

611

uint8_t v1;

sys/arch/arm/arm/fault.c

622

rv = badaddr_read_1(addr, &u.v1);

sys/arch/arm/arm/fault.c

624

*(uint8_t *) rptr = u.v1;

sys/arch/armv7/omap/ommmc.c

880

uint32_t v0,v1,v2,v3;

sys/arch/armv7/omap/ommmc.c

882

v1 = HREAD4(sc, MMCHS_RSP32);

sys/arch/armv7/omap/ommmc.c

886

cmd->c_resp[0] = (v0 >> 8) | ((v1 & 0xff) << 24);

sys/arch/armv7/omap/ommmc.c

887

cmd->c_resp[1] = (v1 >> 8) | ((v2 & 0xff) << 24);

sys/arch/i386/isa/clock.c

238

int v1, v2, v3;

sys/arch/i386/isa/clock.c

248

v1 = inb(IO_TIMER1 + TIMER_CNTR0);

sys/arch/i386/isa/clock.c

249

v1 |= inb(IO_TIMER1 + TIMER_CNTR0) << 8;

sys/arch/i386/isa/clock.c

257

if (v1 >= v2 && v2 >= v3 && v1 - v3 < 0x200)

sys/arch/i386/isa/clock.c

267

if (v1 < v2)

sys/arch/i386/isa/clock.c

268

_swap_val(v1, v2);

sys/arch/i386/isa/clock.c

271

if (v1 < v2)

sys/arch/i386/isa/clock.c

272

_swap_val(v1, v2);

sys/arch/i386/isa/clock.c

275

if (v1 - v3 < 0x200)

sys/arch/i386/isa/clock.c

278

w2 = v3 - v1 + TIMER_DIV(hz);

sys/arch/i386/isa/clock.c

279

w3 = v1 - v2;

sys/arch/i386/isa/clock.c

282

return (v1);

sys/arch/mips64/include/cpustate.h

120

RESTORE_REG(v1, V1, frame, bo) ;\

sys/arch/mips64/include/cpustate.h

51

SAVE_REG(v1, V1, frame, bo) ;\

sys/arch/mips64/include/cpustate.h

78

mfhi v1 ;\

sys/arch/mips64/include/cpustate.h

80

SAVE_REG(v1, MULHI, frame, bo) ;\

sys/arch/mips64/include/cpustate.h

87

GET_CPU_INFO(v0, v1) ;\

sys/arch/mips64/include/frame.h

39

register_t v1;

sys/arch/mips64/mips64/db_machdep.c

92

{ "v1", (long *)&ddb_regs.v1, FCN_NULL },

sys/dev/acpi/acpihpet.c

211

uint32_t v1, v2;

sys/dev/acpi/acpihpet.c

247

v1 = bus_space_read_4(sc->sc_iot, sc->sc_ioh, HPET_MAIN_COUNTER);

sys/dev/acpi/acpihpet.c

250

if (v1 == v2) {

sys/dev/acpi/dsdt.c

1982

int op1, int v1,

sys/dev/acpi/dsdt.c

1994

flag = aml_matchtest(tmp->v_integer, v1, op1) &&

sys/dev/ic/qwx.c

7754

struct qrtr_hdr_v1 *v1 = mtod(m, struct qrtr_hdr_v1 *);

sys/dev/ic/qwx.c

7765

letoh32(v1->type), letoh32(v1->size),

sys/dev/ic/qwx.c

7766

letoh32(v1->confirm_rx));

sys/dev/ic/qwx.c

7767

type = letoh32(v1->type);

sys/dev/ic/qwx.c

7768

size = letoh32(v1->size);

sys/dev/ic/qwx.c

7769

confirm_rx = !!letoh32(v1->confirm_rx);

sys/dev/ic/qwx.c

7770

hdrsize = sizeof(*v1);

sys/dev/ic/qwz.c

5237

struct qrtr_hdr_v1 *v1 = mtod(m, struct qrtr_hdr_v1 *);

sys/dev/ic/qwz.c

5248

letoh32(v1->type), letoh32(v1->size),

sys/dev/ic/qwz.c

5249

letoh32(v1->confirm_rx));

sys/dev/ic/qwz.c

5250

type = letoh32(v1->type);

sys/dev/ic/qwz.c

5251

size = letoh32(v1->size);

sys/dev/ic/qwz.c

5252

confirm_rx = !!letoh32(v1->confirm_rx);

sys/dev/ic/qwz.c

5253

hdrsize = sizeof(*v1);

sys/dev/isa/isapnpdebug.c

241

u_char v0, v1, v2, v3;

sys/dev/isa/isapnpdebug.c

256

v1 = isapnp_read_reg(sc,

sys/dev/isa/isapnpdebug.c

258

r->base = (v0 << 8) | v1;

sys/dev/isa/isapnpdebug.c

268

v1 = isapnp_read_reg(sc,

sys/dev/isa/isapnpdebug.c

270

r->base = (v0 << 16) | (v1 << 8);

sys/dev/isa/isapnpdebug.c

276

v1 = isapnp_read_reg(sc,

sys/dev/isa/isapnpdebug.c

278

r->length = (v0 << 16) | (v1 << 8);

sys/dev/isa/isapnpdebug.c

327

v1 = isapnp_read_reg(sc,

sys/dev/isa/isapnpdebug.c

333

r->base = (v0 << 24) | (v1 << 16) | (v2 << 8) | v3;

sys/dev/isa/isapnpdebug.c

339

v1 = isapnp_read_reg(sc,

sys/dev/isa/isapnpdebug.c

345

r->length = (v0 << 24) | (v1 << 16) | (v2 << 8) | v3;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1006

struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1215

struct _SET_VOLTAGE_PARAMETERS v1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1271

struct _ATOM_VOLTAGE_OBJECT_INFO v1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

1277

struct _ATOM_VOLTAGE_OBJECT v1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

894

struct _ATOM_ASIC_SS_ASSIGNMENT v1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

934

if ((ss_assign->v1.ucClockIndication == id) &&

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

935

(clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

937

le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

938

ss->type = ss_assign->v1.ucSpreadSpectrumMode;

sys/dev/pci/drm/amd/amdgpu/amdgpu_atombios.c

939

ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1585

struct gc_info_v1_0 v1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1612

switch (le16_to_cpu(gc_info->v1.header.version_major)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1614

adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1615

adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1616

le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1617

adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1618

adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1619

adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1620

adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1621

adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1622

adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1623

adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1624

adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1625

adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1626

adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1627

adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1628

adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1629

adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1630

le32_to_cpu(gc_info->v1.gc_num_sa_per_se);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1631

adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1632

if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1637

if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1647

if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1689

le16_to_cpu(gc_info->v1.header.version_major),

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1690

le16_to_cpu(gc_info->v1.header.version_minor));

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1697

struct mall_info_v1_0 v1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1722

switch (le16_to_cpu(mall_info->v1.header.version_major)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1725

mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1726

m_s_present = le32_to_cpu(mall_info->v1.m_s_present);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1727

half_use = le32_to_cpu(mall_info->v1.m_half_use);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1746

le16_to_cpu(mall_info->v1.header.version_major),

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1747

le16_to_cpu(mall_info->v1.header.version_minor));

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1754

struct vcn_info_v1_0 v1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1787

switch (le16_to_cpu(vcn_info->v1.header.version_major)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1794

le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1800

le16_to_cpu(vcn_info->v1.header.version_major),

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1801

le16_to_cpu(vcn_info->v1.header.version_minor));

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1808

struct nps_info_v1_0 v1;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1881

switch (le16_to_cpu(nps_info->v1.header.version_major)) {

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1883

mem_ranges = kvcalloc(nps_info->v1.count,

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1888

*nps_type = nps_info->v1.nps_type;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1889

*range_cnt = nps_info->v1.count;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1892

nps_info->v1.instance_info[i].base_address;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1894

nps_info->v1.instance_info[i].limit_address;

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1902

le16_to_cpu(nps_info->v1.header.version_major),

sys/dev/pci/drm/amd/amdgpu/amdgpu_discovery.c

1903

le16_to_cpu(nps_info->v1.header.version_minor));

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

235

ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

300

ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

390

args.v1.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

391

args.v1.ucTransmitterID = amdgpu_encoder->encoder_id;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

392

args.v1.ucEncodeMode = encoder_mode;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

394

args.v1.ucConfig |=

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

399

adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

459

PIXEL_CLOCK_PARAMETERS v1;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

607

args.v1.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

608

args.v1.usRefDiv = cpu_to_le16(ref_div);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

609

args.v1.usFbDiv = cpu_to_le16(fb_div);

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

610

args.v1.ucFracFbDiv = frac_fb_div;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

611

args.v1.ucPostDiv = post_div;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

612

args.v1.ucPpll = pll_id;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

613

args.v1.ucCRTC = crtc_id;

sys/dev/pci/drm/amd/amdgpu/atombios_crtc.c

614

args.v1.ucRefDivSrc = 1;

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

110

recv_bytes = args.v1.ucDataOutLen;

sys/dev/pci/drm/amd/amdgpu/atombios_dp.c

54

PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1165

args.v1.ucAction = action;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1185

EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1236

args.v1.sDigEncoder.ucAction = action;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1237

args.v1.sDigEncoder.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1238

args.v1.sDigEncoder.ucEncoderMode =

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1241

if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1243

args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1244

args.v1.sDigEncoder.ucLaneNum = dp_lane_count;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1246

args.v1.sDigEncoder.ucLaneNum = 8;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1248

args.v1.sDigEncoder.ucLaneNum = 4;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1427

SELECT_CRTC_SOURCE_PS_ALLOCATION v1;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1454

args.v1.ucCRTC = amdgpu_crtc->crtc_id;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1458

args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1463

args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1465

args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1470

args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1475

args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1477

args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1479

args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1484

args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1486

args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

1488

args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

552

DIG_ENCODER_CONTROL_PS_ALLOCATION v1;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

598

args.v1.ucAction = action;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

599

args.v1.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

603

args.v1.ucEncoderMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

605

if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

606

args.v1.ucLaneNum = dp_lane_count;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

608

args.v1.ucLaneNum = 8;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

610

args.v1.ucLaneNum = 4;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

612

if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

613

args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

616

args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

620

args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

623

args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

627

args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

629

args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

648

args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

669

args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

671

args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

673

args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

675

args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

740

DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

825

args.v1.ucAction = action;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

827

args.v1.usInitInfo = cpu_to_le16(connector_object_id);

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

829

args.v1.asMode.ucLaneSel = lane_num;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

830

args.v1.asMode.ucLaneSet = lane_set;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

833

args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

835

args.v1.usPixelClock = cpu_to_le16((amdgpu_encoder->pixel_clock / 2) / 10);

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

837

args.v1.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

840

args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

843

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

845

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

848

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

850

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

853

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

856

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;

sys/dev/pci/drm/amd/amdgpu/atombios_encoders.c

858

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

645

uint32_t v0, v1, v28, v31;

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

654

v1 = REG_GET_FIELD(hw_assert_msklo,

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

661

if (v0 && v1 && v28 && v31)

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

663

else if (!v0 && !v1 && !v28 && !v31)

sys/dev/pci/drm/amd/amdgpu/df_v3_6.c

667

v0, v1, v28, v31);

sys/dev/pci/drm/amd/amdgpu/df_v4_3.c

32

uint32_t v0, v1, v28, v31;

sys/dev/pci/drm/amd/amdgpu/df_v4_3.c

41

v1 = REG_GET_FIELD(hw_assert_msklo,

sys/dev/pci/drm/amd/amdgpu/df_v4_3.c

48

if (v0 && v1 && v28 && v31)

sys/dev/pci/drm/amd/amdgpu/df_v4_3.c

50

else if (!v0 && !v1 && !v28 && !v31)

sys/dev/pci/drm/amd/amdgpu/df_v4_3.c

54

v0, v1, v28, v31);

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

157

uint32_t v1 = 0;

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

167

v1 = get_reg_field_value(

sys/dev/pci/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

184

if (h1 == h2 && v1 == v2)

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1412

#define AUX_REG_UPDATE_2(reg, f1, v1, f2, v2) \

sys/dev/pci/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

1414

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_math.c

101

return dcn_bw_max3(v1, v2, v3) > dcn_bw_max2(v4, v5) ? dcn_bw_max3(v1, v2, v3) : dcn_bw_max2(v4, v5);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_math.c

94

float dcn_bw_max3(float v1, float v2, float v3)

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_math.c

96

return v3 > dcn_bw_max2(v1, v2) ? v3 : dcn_bw_max2(v1, v2);

sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calc_math.c

99

float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c

69

double math_max3(double v1, double v2, double v3)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c

71

return v3 > math_max2(v1, v2) ? v3 : math_max2(v1, v2);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c

74

double math_max4(double v1, double v2, double v3, double v4)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c

76

return v4 > math_max3(v1, v2, v3) ? v4 : math_max3(v1, v2, v3);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c

79

double math_max5(double v1, double v2, double v3, double v4, double v5)

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c

81

return math_max3(v1, v2, v3) > math_max2(v4, v5) ? math_max3(v1, v2, v3) : math_max2(v4, v5);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.h

15

double math_max3(double v1, double v2, double v3);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.h

16

double math_max4(double v1, double v2, double v3, double v4);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.h

17

double math_max5(double v1, double v2, double v3, double v4, double v5);

sys/dev/pci/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h

705

} v1;

sys/dev/pci/drm/amd/display/dc/inc/bw_fixed.h

54

static inline struct bw_fixed bw_min3(struct bw_fixed v1,

sys/dev/pci/drm/amd/display/dc/inc/bw_fixed.h

58

return bw_min2(bw_min2(v1, v2), v3);

sys/dev/pci/drm/amd/display/dc/inc/bw_fixed.h

61

static inline struct bw_fixed bw_max3(struct bw_fixed v1,

sys/dev/pci/drm/amd/display/dc/inc/bw_fixed.h

65

return bw_max2(bw_max2(v1, v2), v3);

sys/dev/pci/drm/amd/display/dc/inc/dcn_calc_math.h

37

float dcn_bw_max3(float v1, float v2, float v3);

sys/dev/pci/drm/amd/display/dc/inc/dcn_calc_math.h

38

float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5);

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

104

#define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

107

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

115

#define REG_SET_8(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

118

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

127

#define REG_SET_9(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

130

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

140

#define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

143

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

160

#define REG_GET_2(reg_name, f1, v1, f2, v2) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

162

FN(reg_name, f1), v1, \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

165

#define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

167

FN(reg_name, f1), v1, \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

171

#define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

173

FN(reg_name, f1), v1, \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

178

#define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

180

FN(reg_name, f1), v1, \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

186

#define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

188

FN(reg_name, f1), v1, \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

195

#define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

197

FN(reg_name, f1), v1, \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

205

#define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

207

FN(reg_name, f1), v1, \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

234

#define REG_UPDATE_2(reg, f1, v1, f2, v2) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

236

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

239

#define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

241

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

245

#define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

247

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

252

#define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

254

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

260

#define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

262

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

269

#define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

271

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

279

#define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

281

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

290

#define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

292

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

302

#define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

304

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

315

#define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

318

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

333

#define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

336

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

356

#define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

359

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

382

#define REG_UPDATE_SEQ_2(reg, f1, v1, f2, v2) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

383

{ uint32_t val = REG_UPDATE(reg, f1, v1); \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

386

#define REG_UPDATE_SEQ_3(reg, f1, v1, f2, v2, f3, v3) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

387

{ uint32_t val = REG_UPDATE(reg, f1, v1); \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

452

#define IX_REG_SET_2(index_reg_name, data_reg_name, index, init_value, f1, v1, f2, v2) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

454

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

476

#define IX_REG_UPDATE_2(index_reg_name, data_reg_name, index, f1, v1, f2, v2) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

478

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

511

#define IX_REG_SET_SYNC(index, init_value, f1, v1) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

513

FN(reg, f1), v1)

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

515

#define IX_REG_SET_2_SYNC(index, init_value, f1, v1, f2, v2) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

517

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

67

#define REG_SET_2(reg, init_value, f1, v1, f2, v2) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

69

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

72

#define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

74

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

78

#define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

80

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

85

#define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

88

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

94

#define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \

sys/dev/pci/drm/amd/display/dc/inc/reg_helper.h

97

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

103

#define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

105

FN(reg, f1), v1, \

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

65

#define REG_SET_2(reg, init_value, f1, v1, f2, v2) \

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

67

FN(reg, f1), v1, \

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

70

#define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

72

FN(reg, f1), v1, \

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

76

#define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

78

FN(reg, f1), v1, \

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

92

#define REG_UPDATE_2(reg, f1, v1, f2, v2) \

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

94

FN(reg, f1), v1,\

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

97

#define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \

sys/dev/pci/drm/amd/display/dmub/src/dmub_reg.h

99

FN(reg, f1), v1, \

sys/dev/pci/drm/amd/pm/legacy-dpm/kv_dpm.c

2631

struct _ATOM_PPLIB_STATE v1;

sys/dev/pci/drm/amd/pm/legacy-dpm/si_dpm.c

7306

struct _ATOM_PPLIB_STATE v1;

sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomctrl.c

41

struct _ATOM_VOLTAGE_OBJECT_INFO v1;

sys/dev/pci/drm/i915/display/intel_dmc.c

1060

const struct intel_dmc_header_v1 *v1 =

sys/dev/pci/drm/i915/display/intel_dmc.c

1066

mmioaddr = v1->mmioaddr;

sys/dev/pci/drm/i915/display/intel_dmc.c

1067

mmiodata = v1->mmiodata;

sys/dev/pci/drm/i915/display/intel_dmc.c

1068

mmio_count = v1->mmio_count;

sys/dev/pci/drm/i915/display/intel_dmc.c

1072

dmc_header_size = sizeof(*v1);

sys/dev/pci/drm/radeon/atombios_crtc.c

438

ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;

sys/dev/pci/drm/radeon/atombios_crtc.c

519

args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);

sys/dev/pci/drm/radeon/atombios_crtc.c

520

args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;

sys/dev/pci/drm/radeon/atombios_crtc.c

521

args.v1.ucSpreadSpectrumStep = ss->step;

sys/dev/pci/drm/radeon/atombios_crtc.c

522

args.v1.ucSpreadSpectrumDelay = ss->delay;

sys/dev/pci/drm/radeon/atombios_crtc.c

523

args.v1.ucSpreadSpectrumRange = ss->range;

sys/dev/pci/drm/radeon/atombios_crtc.c

524

args.v1.ucPpll = pll_id;

sys/dev/pci/drm/radeon/atombios_crtc.c

525

args.v1.ucEnable = enable;

sys/dev/pci/drm/radeon/atombios_crtc.c

553

ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;

sys/dev/pci/drm/radeon/atombios_crtc.c

687

args.v1.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/pci/drm/radeon/atombios_crtc.c

688

args.v1.ucTransmitterID = radeon_encoder->encoder_id;

sys/dev/pci/drm/radeon/atombios_crtc.c

689

args.v1.ucEncodeMode = encoder_mode;

sys/dev/pci/drm/radeon/atombios_crtc.c

691

args.v1.ucConfig |=

sys/dev/pci/drm/radeon/atombios_crtc.c

696

adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;

sys/dev/pci/drm/radeon/atombios_crtc.c

756

PIXEL_CLOCK_PARAMETERS v1;

sys/dev/pci/drm/radeon/atombios_crtc.c

847

args.v1.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/pci/drm/radeon/atombios_crtc.c

848

args.v1.usRefDiv = cpu_to_le16(ref_div);

sys/dev/pci/drm/radeon/atombios_crtc.c

849

args.v1.usFbDiv = cpu_to_le16(fb_div);

sys/dev/pci/drm/radeon/atombios_crtc.c

850

args.v1.ucFracFbDiv = frac_fb_div;

sys/dev/pci/drm/radeon/atombios_crtc.c

851

args.v1.ucPostDiv = post_div;

sys/dev/pci/drm/radeon/atombios_crtc.c

852

args.v1.ucPpll = pll_id;

sys/dev/pci/drm/radeon/atombios_crtc.c

853

args.v1.ucCRTC = crtc_id;

sys/dev/pci/drm/radeon/atombios_crtc.c

854

args.v1.ucRefDivSrc = 1;

sys/dev/pci/drm/radeon/atombios_dp.c

107

args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));

sys/dev/pci/drm/radeon/atombios_dp.c

108

args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));

sys/dev/pci/drm/radeon/atombios_dp.c

109

args.v1.ucDataOutLen = 0;

sys/dev/pci/drm/radeon/atombios_dp.c

110

args.v1.ucChannelID = chan->rec.i2c_id;

sys/dev/pci/drm/radeon/atombios_dp.c

111

args.v1.ucDelay = delay / 10;

sys/dev/pci/drm/radeon/atombios_dp.c

117

*ack = args.v1.ucReplyStatus;

sys/dev/pci/drm/radeon/atombios_dp.c

120

if (args.v1.ucReplyStatus == 1) {

sys/dev/pci/drm/radeon/atombios_dp.c

127

if (args.v1.ucReplyStatus == 2) {

sys/dev/pci/drm/radeon/atombios_dp.c

134

if (args.v1.ucReplyStatus == 3) {

sys/dev/pci/drm/radeon/atombios_dp.c

140

recv_bytes = args.v1.ucDataOutLen;

sys/dev/pci/drm/radeon/atombios_dp.c

81

PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;

sys/dev/pci/drm/radeon/atombios_encoders.c

1078

args.v1.ucAction = action;

sys/dev/pci/drm/radeon/atombios_encoders.c

1080

args.v1.usInitInfo = cpu_to_le16(connector_object_id);

sys/dev/pci/drm/radeon/atombios_encoders.c

1082

args.v1.asMode.ucLaneSel = lane_num;

sys/dev/pci/drm/radeon/atombios_encoders.c

1083

args.v1.asMode.ucLaneSet = lane_set;

sys/dev/pci/drm/radeon/atombios_encoders.c

1086

args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);

sys/dev/pci/drm/radeon/atombios_encoders.c

1088

args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);

sys/dev/pci/drm/radeon/atombios_encoders.c

1090

args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);

sys/dev/pci/drm/radeon/atombios_encoders.c

1093

args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;

sys/dev/pci/drm/radeon/atombios_encoders.c

1096

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;

sys/dev/pci/drm/radeon/atombios_encoders.c

1098

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;

sys/dev/pci/drm/radeon/atombios_encoders.c

1105

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;

sys/dev/pci/drm/radeon/atombios_encoders.c

1107

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;

sys/dev/pci/drm/radeon/atombios_encoders.c

1109

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;

sys/dev/pci/drm/radeon/atombios_encoders.c

1111

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;

sys/dev/pci/drm/radeon/atombios_encoders.c

1114

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;

sys/dev/pci/drm/radeon/atombios_encoders.c

1116

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;

sys/dev/pci/drm/radeon/atombios_encoders.c

1121

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;

sys/dev/pci/drm/radeon/atombios_encoders.c

1123

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;

sys/dev/pci/drm/radeon/atombios_encoders.c

1126

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;

sys/dev/pci/drm/radeon/atombios_encoders.c

1129

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;

sys/dev/pci/drm/radeon/atombios_encoders.c

1131

args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;

sys/dev/pci/drm/radeon/atombios_encoders.c

1398

args.v1.ucAction = action;

sys/dev/pci/drm/radeon/atombios_encoders.c

1418

EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;

sys/dev/pci/drm/radeon/atombios_encoders.c

1469

args.v1.sDigEncoder.ucAction = action;

sys/dev/pci/drm/radeon/atombios_encoders.c

1470

args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);

sys/dev/pci/drm/radeon/atombios_encoders.c

1471

args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);

sys/dev/pci/drm/radeon/atombios_encoders.c

1473

if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {

sys/dev/pci/drm/radeon/atombios_encoders.c

1475

args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;

sys/dev/pci/drm/radeon/atombios_encoders.c

1476

args.v1.sDigEncoder.ucLaneNum = dp_lane_count;

sys/dev/pci/drm/radeon/atombios_encoders.c

1478

args.v1.sDigEncoder.ucLaneNum = 8;

sys/dev/pci/drm/radeon/atombios_encoders.c

1480

args.v1.sDigEncoder.ucLaneNum = 4;

sys/dev/pci/drm/radeon/atombios_encoders.c

1840

SELECT_CRTC_SOURCE_PS_ALLOCATION v1;

sys/dev/pci/drm/radeon/atombios_encoders.c

1867

args.v1.ucCRTC = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/atombios_encoders.c

1870

args.v1.ucCRTC = radeon_crtc->crtc_id;

sys/dev/pci/drm/radeon/atombios_encoders.c

1872

args.v1.ucCRTC = radeon_crtc->crtc_id << 2;

sys/dev/pci/drm/radeon/atombios_encoders.c

1877

args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;

sys/dev/pci/drm/radeon/atombios_encoders.c

1882

args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;

sys/dev/pci/drm/radeon/atombios_encoders.c

1884

args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;

sys/dev/pci/drm/radeon/atombios_encoders.c

1889

args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;

sys/dev/pci/drm/radeon/atombios_encoders.c

1894

args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;

sys/dev/pci/drm/radeon/atombios_encoders.c

1896

args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;

sys/dev/pci/drm/radeon/atombios_encoders.c

1898

args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;

sys/dev/pci/drm/radeon/atombios_encoders.c

1903

args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;

sys/dev/pci/drm/radeon/atombios_encoders.c

1905

args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;

sys/dev/pci/drm/radeon/atombios_encoders.c

1907

args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;

sys/dev/pci/drm/radeon/atombios_encoders.c

553

LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;

sys/dev/pci/drm/radeon/atombios_encoders.c

601

args.v1.ucMisc = 0;

sys/dev/pci/drm/radeon/atombios_encoders.c

602

args.v1.ucAction = action;

sys/dev/pci/drm/radeon/atombios_encoders.c

604

args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;

sys/dev/pci/drm/radeon/atombios_encoders.c

605

args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);

sys/dev/pci/drm/radeon/atombios_encoders.c

608

args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;

sys/dev/pci/drm/radeon/atombios_encoders.c

610

args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;

sys/dev/pci/drm/radeon/atombios_encoders.c

613

args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;

sys/dev/pci/drm/radeon/atombios_encoders.c

615

args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;

sys/dev/pci/drm/radeon/atombios_encoders.c

617

args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;

sys/dev/pci/drm/radeon/atombios_encoders.c

824

DIG_ENCODER_CONTROL_PS_ALLOCATION v1;

sys/dev/pci/drm/radeon/atombios_encoders.c

877

args.v1.ucAction = action;

sys/dev/pci/drm/radeon/atombios_encoders.c

878

args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);

sys/dev/pci/drm/radeon/atombios_encoders.c

882

args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);

sys/dev/pci/drm/radeon/atombios_encoders.c

884

if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))

sys/dev/pci/drm/radeon/atombios_encoders.c

885

args.v1.ucLaneNum = dp_lane_count;

sys/dev/pci/drm/radeon/atombios_encoders.c

887

args.v1.ucLaneNum = 8;

sys/dev/pci/drm/radeon/atombios_encoders.c

889

args.v1.ucLaneNum = 4;

sys/dev/pci/drm/radeon/atombios_encoders.c

893

args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;

sys/dev/pci/drm/radeon/atombios_encoders.c

897

args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;

sys/dev/pci/drm/radeon/atombios_encoders.c

900

args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;

sys/dev/pci/drm/radeon/atombios_encoders.c

904

args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;

sys/dev/pci/drm/radeon/atombios_encoders.c

906

args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;

sys/dev/pci/drm/radeon/atombios_encoders.c

908

if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))

sys/dev/pci/drm/radeon/atombios_encoders.c

909

args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;

sys/dev/pci/drm/radeon/atombios_encoders.c

929

args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;

sys/dev/pci/drm/radeon/atombios_encoders.c

953

args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;

sys/dev/pci/drm/radeon/atombios_encoders.c

955

args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;

sys/dev/pci/drm/radeon/atombios_encoders.c

957

args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;

sys/dev/pci/drm/radeon/atombios_encoders.c

959

args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;

sys/dev/pci/drm/radeon/atombios_encoders.c

993

DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;

sys/dev/pci/drm/radeon/ci_dpm.c

5391

struct _ATOM_PPLIB_STATE v1;

sys/dev/pci/drm/radeon/kv_dpm.c

2366

struct _ATOM_PPLIB_STATE v1;

sys/dev/pci/drm/radeon/ni_dpm.c

3890

struct _ATOM_PPLIB_STATE v1;

sys/dev/pci/drm/radeon/ni_dpm.c

4017

(power_state->v1.ucNonClockStateIndex *

sys/dev/pci/drm/radeon/ni_dpm.c

4030

idx = (u8 *)&power_state->v1.ucClockStateIndices[0];

sys/dev/pci/drm/radeon/radeon_atombios.c

1504

struct _ATOM_ASIC_SS_ASSIGNMENT v1;

sys/dev/pci/drm/radeon/radeon_atombios.c

1544

if ((ss_assign->v1.ucClockIndication == id) &&

sys/dev/pci/drm/radeon/radeon_atombios.c

1545

(clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {

sys/dev/pci/drm/radeon/radeon_atombios.c

1547

le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);

sys/dev/pci/drm/radeon/radeon_atombios.c

1548

ss->type = ss_assign->v1.ucSpreadSpectrumMode;

sys/dev/pci/drm/radeon/radeon_atombios.c

1549

ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);

sys/dev/pci/drm/radeon/radeon_atombios.c

2041

struct _ATOM_PPLIB_STATE v1;

sys/dev/pci/drm/radeon/radeon_atombios.c

2617

(power_state->v1.ucNonClockStateIndex *

sys/dev/pci/drm/radeon/radeon_atombios.c

2631

(power_state->v1.ucClockStateIndices[j] *

sys/dev/pci/drm/radeon/radeon_atombios.c

2834

struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;

sys/dev/pci/drm/radeon/radeon_atombios.c

2862

args.v1.ucAction = clock_type;

sys/dev/pci/drm/radeon/radeon_atombios.c

2863

args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */

sys/dev/pci/drm/radeon/radeon_atombios.c

2867

dividers->post_div = args.v1.ucPostDiv;

sys/dev/pci/drm/radeon/radeon_atombios.c

2868

dividers->fb_div = args.v1.ucFbDiv;

sys/dev/pci/drm/radeon/radeon_atombios.c

3108

struct _SET_VOLTAGE_PARAMETERS v1;

sys/dev/pci/drm/radeon/radeon_atombios.c

3128

args.v1.ucVoltageType = voltage_type;

sys/dev/pci/drm/radeon/radeon_atombios.c

3129

args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;

sys/dev/pci/drm/radeon/radeon_atombios.c

3130

args.v1.ucVoltageIndex = volt_index;

sys/dev/pci/drm/radeon/radeon_atombios.c

3387

struct _ATOM_VOLTAGE_OBJECT_INFO v1;

sys/dev/pci/drm/radeon/radeon_atombios.c

3393

struct _ATOM_VOLTAGE_OBJECT v1;

sys/dev/pci/drm/radeon/radeon_atombios.c

3398

static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,

sys/dev/pci/drm/radeon/radeon_atombios.c

3401

u32 size = le16_to_cpu(v1->sHeader.usStructureSize);

sys/dev/pci/drm/radeon/radeon_atombios.c

3403

u8 *start = (u8 *)v1;

sys/dev/pci/drm/radeon/radeon_atombios.c

3470

atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);

sys/dev/pci/drm/radeon/radeon_atombios.c

3472

(voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))

sys/dev/pci/drm/radeon/radeon_atombios.c

3569

atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);

sys/dev/pci/drm/radeon/radeon_atombios.c

3572

&voltage_object->v1.asFormula;

sys/dev/pci/drm/radeon/radeon_atombios.c

3628

atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);

sys/dev/pci/drm/radeon/radeon_atombios.c

3631

&voltage_object->v1.asFormula;

sys/dev/pci/drm/radeon/radeon_atombios.c

3678

atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);

sys/dev/pci/drm/radeon/radeon_atombios.c

3681

&voltage_object->v1.asFormula;

sys/dev/pci/drm/radeon/rs780_dpm.c

713

struct _ATOM_PPLIB_STATE v1;

sys/dev/pci/drm/radeon/rs780_dpm.c

821

(power_state->v1.ucNonClockStateIndex *

sys/dev/pci/drm/radeon/rs780_dpm.c

827

(power_state->v1.ucClockStateIndices[0] *

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1790

struct _ATOM_PPLIB_STATE v1;

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1904

(power_state->v1.ucNonClockStateIndex *

sys/dev/pci/drm/radeon/rv6xx_dpm.c

1916

idx = (u8 *)&power_state->v1.ucClockStateIndices[0];

sys/dev/pci/drm/radeon/rv770_dpm.c

2141

struct _ATOM_PPLIB_STATE v1;

sys/dev/pci/drm/radeon/rv770_dpm.c

2300

(power_state->v1.ucNonClockStateIndex *

sys/dev/pci/drm/radeon/rv770_dpm.c

2313

idx = (u8 *)&power_state->v1.ucClockStateIndices[0];

sys/dev/pci/drm/radeon/si_dpm.c

6645

struct _ATOM_PPLIB_STATE v1;

sys/dev/pci/drm/radeon/sumo_dpm.c

1386

struct _ATOM_PPLIB_STATE v1;

sys/dev/pci/drm/radeon/trinity_dpm.c

1628

struct _ATOM_PPLIB_STATE v1;

sys/dev/pci/if_bnxtreg.h

7434

uint8_t v1;

sys/dev/pci/if_bnxtreg.h

7739

uint8_t v1;

sys/dev/pci/if_bnxtreg.h

8799

uint8_t v1;

sys/dev/pci/if_bnxtreg.h

9155

uint8_t v1;

sys/dev/pci/if_iwm.c

4643

energy_a = desc->v1.energy_a;

sys/dev/pci/if_iwm.c

4644

energy_b = desc->v1.energy_b;

sys/dev/pci/if_iwm.c

5463

rate_n_flags = le32toh(desc->v1.rate_n_flags);

sys/dev/pci/if_iwm.c

5464

chanidx = desc->v1.channel;

sys/dev/pci/if_iwm.c

5465

device_timestamp = desc->v1.gp2_on_air_rise;

sys/dev/pci/if_iwm.c

5472

rxi.rxi_tstamp = le64toh(desc->v1.tsf_on_air_rise);

sys/dev/pci/if_iwm.c

7938

return &req->v1.channel;

sys/dev/pci/if_iwm.c

7950

return (void *)&req->v1.data;

sys/dev/pci/if_iwm.c

8025

req->v1.active_dwell = 10;

sys/dev/pci/if_iwm.c

8026

req->v1.passive_dwell = 110;

sys/dev/pci/if_iwm.c

8027

req->v1.fragmented_dwell = 44;

sys/dev/pci/if_iwm.c

8028

req->v1.extended_dwell = 90;

sys/dev/pci/if_iwm.c

8030

req->v1.scan_priority = htole32(IWM_SCAN_PRIORITY_HIGH);

sys/dev/pci/if_iwm.c

8044

req->v1.max_out_time = timeout;

sys/dev/pci/if_iwm.c

8045

req->v1.suspend_time = timeout;

sys/dev/pci/if_iwmreg.h

1036

} v1;

sys/dev/pci/if_iwmreg.h

3392

struct iwm_rx_mpdu_desc_v1 v1;

sys/dev/pci/if_iwmreg.h

5875

} v1; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */

sys/dev/pci/if_iwx.c

4662

energy_a = desc->v1.energy_a;

sys/dev/pci/if_iwx.c

4663

energy_b = desc->v1.energy_b;

sys/dev/pci/if_iwx.c

5322

rate_n_flags = le32toh(desc->v1.rate_n_flags);

sys/dev/pci/if_iwx.c

5323

chanidx = desc->v1.channel;

sys/dev/pci/if_iwx.c

5324

device_timestamp = le32toh(desc->v1.gp2_on_air_rise);

sys/dev/pci/if_iwx.c

7207

chan->v1.channel_num = channel_num;

sys/dev/pci/if_iwx.c

7208

chan->v1.iter_count = 1;

sys/dev/pci/if_iwx.c

7209

chan->v1.iter_interval = htole16(0);

sys/dev/pci/if_iwxreg.h

1558

} v1;

sys/dev/pci/if_iwxreg.h

3813

struct iwx_rx_mpdu_desc_v1 v1;

sys/dev/pci/if_iwxreg.h

7687

} v1; /* SCAN_CHANNEL_CFG_S_VER1 */

sys/dev/pci/if_iwxreg.h

7831

} v1; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */

sys/dev/pci/if_mwx.c

4389

u32 v0, v1;

sys/dev/pci/if_mwx.c

4396

v1 = le32_to_cpu(rxv[1]);

sys/dev/pci/if_mwx.c

4402

status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1);

sys/dev/pci/if_mwx.c

4403

status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1);

sys/dev/pci/if_mwx.c

4404

status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1);

sys/dev/pci/if_mwx.c

4405

status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1);

sys/dev/pci/if_ocereg.h

1984

} v1;

sys/lib/libkern/muldi3.c

120

if (u1 == 0 && v1 == 0) {

sys/lib/libkern/muldi3.c

140

if (v0 >= v1)

sys/lib/libkern/muldi3.c

141

vdiff = v0 - v1;

sys/lib/libkern/muldi3.c

143

vdiff = v1 - v0, negmid ^= 1;

sys/lib/libkern/muldi3.c

146

high = u1 * v1;

sys/lib/libkern/muldi3.c

182

u_int u1, u0, v1, v0, udiff, vdiff, high, mid, low;

sys/lib/libkern/muldi3.c

189

v1 = HHALF(v);

sys/lib/libkern/muldi3.c

195

if (u1 == 0 && v1 == 0)

sys/lib/libkern/muldi3.c

202

if (v0 >= v1)

sys/lib/libkern/muldi3.c

203

vdiff = v0 - v1;

sys/lib/libkern/muldi3.c

205

vdiff = v1 - v0, neg ^= 1;

sys/lib/libkern/muldi3.c

208

high = u1 * v1;

sys/lib/libkern/qdivrem.c

175

v1 = v[1]; /* for D3 -- note that v[1..n] are constant */

sys/lib/libkern/qdivrem.c

191

if (uj0 == v1) {

sys/lib/libkern/qdivrem.c

197

qhat = nn / v1;

sys/lib/libkern/qdivrem.c

198

rhat = nn % v1;

sys/lib/libkern/qdivrem.c

203

if ((rhat += v1) >= B)

sys/lib/libkern/qdivrem.c

68

digit v1, v2;

usr.bin/at/at.c

375

byctime(const void *v1, const void *v2)

usr.bin/at/at.c

377

const struct atjob *j1 = *(const struct atjob **)v1;

usr.bin/at/at.c

385

byjobno(const void *v1, const void *v2)

usr.bin/at/at.c

387

const struct atjob *j1 = *(struct atjob **)v1;

usr.bin/calendar/day.c

267

int day = 0, flags = 0, month = 0, v1, v2, i;

usr.bin/calendar/day.c

287

if (!(v1 = getfield(endp, &endp, &flags)))

usr.bin/calendar/day.c

296

vwd = v1;

usr.bin/calendar/day.c

303

else if (flags & F_ISDAY || v1 > 12) {

usr.bin/calendar/day.c

306

day = v1;

usr.bin/calendar/day.c

336

month = v1;

usr.bin/calendar/day.c

363

day = v1;

usr.bin/calendar/day.c

375

month = v1;

usr.bin/calendar/day.c

427

if (((v1 = offset + f_dayAfter) < 50) && (interval == YEARLY)) {

usr.bin/calendar/day.c

446

if ((v2 > v1) || (v2 < 0)) {

usr.bin/calendar/day.c

448

<= v1)

usr.bin/calendar/day.c

474

v1 = vwd % (NUMEV + 1) - 1;

usr.bin/calendar/day.c

476

if (v1 < 0) {

usr.bin/calendar/day.c

477

v1 += NUMEV + 1;

usr.bin/calendar/day.c

516

v1 = vwd;

usr.bin/calendar/day.c

517

variable_weekday(&v1, tmtmp.tm_mon + 1,

usr.bin/calendar/day.c

519

tmtmp.tm_mday = v1;

usr.bin/calendar/day.c

528

tmtmp.tm_mday = spev[v1].getev(tmtmp.tm_year +

usr.bin/calendar/day.c

531

v1 = vwd;

usr.bin/calendar/day.c

532

variable_weekday(&v1, tmtmp.tm_mon + 1,

usr.bin/calendar/day.c

534

tmtmp.tm_mday = v1;

usr.bin/calendar/day.c

673

int v1, v2;

usr.bin/calendar/day.c

684

v1 = *day/10 - 1; /* offset -4 ... -1 */

usr.bin/calendar/day.c

692

(v1 + 1) * 7 - (v2 - *day + 7) % 7;

usr.bin/calendar/day.c

700

v1 = *day/10; /* offset */

usr.bin/calendar/day.c

707

*day = 1 + (v1 - 1) * 7 + (*day - v2 + 7) % 7;

usr.bin/cdio/rip.c

185

u_char v1, v2, v3;

usr.bin/cdio/rip.c

189

v1 = (u_char)val1;

usr.bin/cdio/rip.c

194

if (v1 > v2) {

usr.bin/cdio/rip.c

195

v3 = v1;

usr.bin/cdio/rip.c

196

v1 = v2;

usr.bin/cdio/rip.c

203

if (v1 + 1 == entry->start || v1 == entry->start)

usr.bin/cdio/rip.c

205

else if (v1 > entry->start && v1 <= entry->end + 1)

usr.bin/cdio/rip.c

216

if (v1 < entry->start)

usr.bin/cdio/rip.c

217

entry->start = v1;

usr.bin/cdio/rip.c

229

tp->start = v1;

usr.bin/dig/lib/isc/timer.c

381

sooner(void *v1, void *v2) {

usr.bin/dig/lib/isc/timer.c

384

t1 = v1;

usr.bin/gprof/arcs.c

100

const nltype * const *npp1 = v1;

usr.bin/gprof/arcs.c

98

topcmp(const void *v1, const void *v2)

usr.bin/gprof/printgprof.c

234

totalcmp(const void *v1, const void *v2)

usr.bin/gprof/printgprof.c

236

const nltype *np1 = *(const nltype **)v1;

usr.bin/gprof/printgprof.c

653

namecmp(const void *v1, const void *v2)

usr.bin/gprof/printgprof.c

655

const nltype * const *npp1 = v1;

usr.bin/gprof/printgprof.c

69

timecmp(const void *v1, const void *v2)

usr.bin/gprof/printgprof.c

71

const nltype * const *npp1 = v1;

usr.bin/mg/interpreter.c

531

struct varentry *v1 = NULL;

usr.bin/mg/interpreter.c

538

SLIST_FOREACH(v1, &varhead, entry) {

usr.bin/mg/interpreter.c

539

if (strcmp(*argp, v1->v_name) == 0) {

usr.bin/mg/interpreter.c

540

(void)(strlcpy(*varbuf, v1->v_buf, sizof) >= sizof);

usr.bin/mg/interpreter.c

572

struct varentry *vt, *v1 = NULL;

usr.bin/mg/interpreter.c

594

SLIST_FOREACH_SAFE(v1, &varhead, entry, vt) {

usr.bin/mg/interpreter.c

595

if (strcmp(vnamep, v1->v_name) == 0) {

usr.bin/mg/interpreter.c

596

SLIST_REMOVE(&varhead, v1, varentry, entry);

usr.bin/mg/interpreter.c

597

free(v1->v_name);

usr.bin/mg/interpreter.c

598

free(v1);

usr.bin/mg/interpreter.c

602

if ((v1 = malloc(sizeof(struct varentry))) == NULL)

usr.bin/mg/interpreter.c

604

if ((v1->v_name = strndup(vnamep, BUFSIZE)) == NULL) {

usr.bin/mg/interpreter.c

605

free(v1);

usr.bin/mg/interpreter.c

608

SLIST_INSERT_HEAD(&varhead, v1, entry);

usr.bin/mg/interpreter.c

609

vnamep = v1->v_name;

usr.bin/mg/interpreter.c

610

v1->v_count = 0;

usr.bin/mg/interpreter.c

611

v1->v_vals = NULL;

usr.bin/mg/interpreter.c

612

v1->v_buf[0] = '\0';

usr.bin/mg/interpreter.c

614

defnam = v1->v_buf;

usr.bin/rdist/expand.c

295

argcmp(const void *v1, const void *v2)

usr.bin/rdist/expand.c

297

const char *const *a1 = v1, *const *a2 = v2;

usr.bin/rup/rup.c

106

compare(const void *v1, const void *v2)

usr.bin/rup/rup.c

108

const struct rup_data *d1 = v1;

usr.bin/ssh/libcrux_mlkem768_sha3.h

6518

int16_t v1 = libcrux_secrets_int_as_i16_59(

usr.bin/ssh/libcrux_mlkem768_sha3.h

6544

.snd = v1,

usr.bin/ssh/sshbuf-misc.c

106

int r, v1, v2;

usr.bin/ssh/sshbuf-misc.c

111

if ((v1 = b16tod(b16[o])) == -1 ||

usr.bin/ssh/sshbuf-misc.c

116

if ((r = sshbuf_put_u8(ret, (u_char)((v1 << 4) | v2))) != 0) {

usr.bin/systat/uvm.c

259

print_uvmexp_field(FLD_VALUE1, FLD_NAME1, l->v1, l->ov1, l->n1);

usr.bin/systat/uvm.c

46

int *v1;

usr.bin/top/machine.c

638

p2 = *(struct kinfo_proc **) v1; \

usr.bin/top/machine.c

640

p1 = *(struct kinfo_proc **) v1; \

usr.bin/top/machine.c

647

compare_cpu(const void *v1, const void *v2)

usr.bin/top/machine.c

666

compare_size(const void *v1, const void *v2)

usr.bin/top/machine.c

685

compare_res(const void *v1, const void *v2)

usr.bin/top/machine.c

704

compare_time(const void *v1, const void *v2)

usr.bin/top/machine.c

723

compare_prio(const void *v1, const void *v2)

usr.bin/top/machine.c

741

compare_pid(const void *v1, const void *v2)

usr.bin/top/machine.c

760

compare_cmd(const void *v1, const void *v2)

usr.bin/vi/common/util.h

49

#define NADD_SLONG(v1, v2) \

usr.bin/vi/common/util.h

50

((v1) < 0 ? \

usr.bin/vi/common/util.h

52

NNFITS(LONG_MIN, (v1), (v2))) ? NUM_UNDER : NUM_OK : \

usr.bin/vi/common/util.h

53

(v1) > 0 ? \

usr.bin/vi/common/util.h

55

NPFITS(LONG_MAX, (v1), (v2)) ? NUM_OK : NUM_OVER : \

usr.sbin/config/main.c

744

optcmp(const void *v1, const void *v2)

usr.sbin/config/main.c

746

const struct opt *sp1 = v1, *sp2 = v2;

usr.sbin/lpr/common_source/common.c

304

compar(const void *v1, const void *v2)

usr.sbin/lpr/common_source/common.c

306

struct queue *p1 = *(struct queue **)v1;

usr.sbin/nsd/siphash.c

154

b = v0 ^ v1 ^ v2 ^ v3;

usr.sbin/nsd/siphash.c

160

v1 ^= 0xdd;

usr.sbin/nsd/siphash.c

166

b = v0 ^ v1 ^ v2 ^ v3;

usr.sbin/nsd/siphash.c

46

v0 += v1; \

usr.sbin/nsd/siphash.c

47

v1 = ROTL(v1, 13); \

usr.sbin/nsd/siphash.c

48

v1 ^= v0; \

usr.sbin/nsd/siphash.c

56

v2 += v1; \

usr.sbin/nsd/siphash.c

57

v1 = ROTL(v1, 17); \

usr.sbin/nsd/siphash.c

58

v1 ^= v2; \

usr.sbin/nsd/siphash.c

67

printf("(%3d) v1 %08x %08x\n", (int)inlen, (uint32_t)(v1 >> 32), \

usr.sbin/nsd/siphash.c

68

(uint32_t)v1); \

usr.sbin/nsd/siphash.c

81

uint64_t v1 = 0x646f72616e646f6dULL;

usr.sbin/nsd/siphash.c

93

v1 ^= k1;

usr.sbin/nsd/siphash.c

98

v1 ^= 0xee;

usr.sbin/quot/quot.c

259

cmpusers(const void *v1, const void *v2)

usr.sbin/quot/quot.c

261

const struct user *u1 = v1, *u2 = v2;

usr.sbin/trpt/trpt.c

414

numeric(const void *v1, const void *v2)

usr.sbin/trpt/trpt.c

416

const caddr_t *c1 = v1;

usr.sbin/unbound/services/view.c

49

view_cmp(const void* v1, const void* v2)

usr.sbin/unbound/services/view.c

51

struct view* a = (struct view*)v1;

usr.sbin/unbound/services/view.h

115

int view_cmp(const void* v1, const void* v2);

usr.sbin/unbound/util/siphash.c

110

v1 ^= k1;

usr.sbin/unbound/util/siphash.c

114

v1 ^= 0xee;

usr.sbin/unbound/util/siphash.c

182

b = v0 ^ v1 ^ v2 ^ v3;

usr.sbin/unbound/util/siphash.c

188

v1 ^= 0xdd;

usr.sbin/unbound/util/siphash.c

194

b = v0 ^ v1 ^ v2 ^ v3;

usr.sbin/unbound/util/siphash.c

58

v0 += v1; \

usr.sbin/unbound/util/siphash.c

59

v1 = ROTL(v1, 13); \

usr.sbin/unbound/util/siphash.c

60

v1 ^= v0; \

usr.sbin/unbound/util/siphash.c

68

v2 += v1; \

usr.sbin/unbound/util/siphash.c

69

v1 = ROTL(v1, 17); \

usr.sbin/unbound/util/siphash.c

70

v1 ^= v2; \

usr.sbin/unbound/util/siphash.c

79

printf("(%3d) v1 %08x %08x\n", (int)inlen, (uint32_t)(v1 >> 32), \

usr.sbin/unbound/util/siphash.c

80

(uint32_t)v1); \

usr.sbin/unbound/util/siphash.c

94

uint64_t v1 = 0x646f72616e646f6dULL;

usr.sbin/vmd/virtio.c

1383

int v1 = (dev->device_feature & VIRTIO_F_VERSION_1) ? 1 : 0;

usr.sbin/vmd/virtio.c

1393

if (v1) {

usr.sbin/vmd/vm_agentx.c

434

const struct vmop_info_result *v1 = c1, *v2 = c2;

usr.sbin/vmd/vm_agentx.c

436

return (v1->vir_id < v2->vir_id ? -1 : v1->vir_id > v2->vir_id);