urtwn_read_4
if (urtwn_read_4(sc, R92C_SYS_CFG) & R92E_SYS_CFG_SPSLDO_SEL) {
reg = urtwn_read_4(sc, R92C_SYS_SWR_CTRL2);
urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xfffffc7f);
urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xffdfffff);
if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
urtwn_read_4(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON);
if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN);
if (!(urtwn_read_4(sc, R92E_AUTO_LLT) & R92E_AUTO_LLT_EN))
reg = urtwn_read_4(sc, R92C_MCUFWDL);
reg = urtwn_read_4(sc, R92C_TDECTRL);
urtwn_read_4(sc, R92C_TXDMA_OFFSET_CHK) |
uint32_t urtwn_read_4(void *, uint16_t);
#define urtwn_bb_read urtwn_read_4
sc->sc_sc.sc_ops.read_4 = urtwn_read_4;
if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) ==