urtwn_bb_read
reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO);
reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO);
reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING);
reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
reg = urtwn_bb_read(sc, 0xe74);
reg = urtwn_bb_read(sc, 0xe78);
reg = urtwn_bb_read(sc, 0xe7c);
reg = urtwn_bb_read(sc, 0xe80);
reg = urtwn_bb_read(sc, 0xe88);
reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL);
reg = urtwn_bb_read(sc, R92C_AFE_CTRL3);
if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR)